CY8C26643-24AXI Cypress Semiconductor Corp, CY8C26643-24AXI Datasheet - Page 60

• Manufacturer Part Number: CY8C26643-24AXI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 428-1645

9.4
Global Inputs and Outputs provide additional capability
to route clock and data signals to the Digital PSoC
blocks. Digital PSoC blocks are connected to the global
input and output lines by configuring the PSoC block
Input
DBA00OU-DCA07OU). These global input and output
lines form an 8-bit global input bus and an 8-bit global
output bus. Four Digital PSoC blocks have access to the
upper half of these buses, while the other four access
the lower half, per the configuration register. These glo-
bal input/output buses may be connected to the I/O pins
on a per-pin basis using the pin configuration registers.
Table 59:
9.4.2
The PSoC block Output Register defines the selection of
the Global Output bus line to be driven by the digital
PSoC blocks. Only 4 of the Global Output bus lines are
available as selections to a given digital PSoC block as
shown in the table below. The Global Output bus has two
functions. Since Global Outputs are also selectable as
inputs to digital PSoC blocks, signals can be routed
between blocks using this bus. In addition, Global Out-
Table 60:
9.5
9.5.1
9.5.1.1
The timer function continuously measures the amount of
time in “ticks” between two events, and provides a rate
60
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
Output [7]
Input [7]
Port x[7]
Port x[7]
Global
Global
and
Global Inputs and Outputs
Available Programmed Digital Functionality
Global Input Assignments
Output Assignments
Global Output Assignments
Timer with Optional Capture
Summary
Output
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
Output [6]
Input [6]
Port x[6]
Port x[6]
Global
Global
registers
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
Output [5]
Input [5]
Port x[5]
Port x[5]
Global
Global
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
(DBA00IN-DCA07IN,
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
Output [4]
Input [4]
Port x[4]
Port x[4]
Global
Global
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
Output [3]
This allows Digital PSoC blocks to route their inputs and
outputs to pins using the global I/O buses.
9.4.1
The PSoC block Input Register defines the selection of
Global Inputs to digital PSoC blocks. Only 4 of the Global
Inputs bus lines are available as selections to a given
digital PSoC block as shown in the table below. Once the
Global Input has been selected using the PSoC block
Input Register selection bits, a GPIO pin must be config-
ured to drive the selected Global Input. This configura-
tion may be set in the GPIO Global Select Register. The
GPIO direction must also be set to input mode by config-
uring the Drive Mode registers to select High Z.
puts may drive out to GPIO pins. In this case, once the
Global Output has been selected using the PSoC block
Output Register selection bits, a GPIO pin must be con-
figured to select the Global Output to drive to the pin.
This configuration may be set in the GPIO Global Select
Register. The GPIO direction must also be set to output
mode (which is the default) by configuring the Drive
Mode registers one of the available driving strengths.
generator. A down counter lies at the heart of the timer
functions. Rate generators divide their clock source by
an integer value. Hardware or software generated events
Input [3]
Port x[3]
Port x[3]
Global
Global
Input Assignments
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
Output [2]
Input [2]
Port x[2]
Port x[2]
Global
Global
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
Output [1]
Input [1]
Port x[1]
Port x[1]
Global
Global
September 5, 2002
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
Output [0]
Input [0]
Port x[0]
Port x[0]
Global
Global