CY8C26643-24AXI Cypress Semiconductor Corp, CY8C26643-24AXI Datasheet - Page 112

• Manufacturer Part Number: CY8C26643-24AXI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 428-1645

11.3
11.3.1 Overview
The microcontroller supports two types of resets. When
reset is initiated, all registers are restored to their default
states and all interrupts are disabled.
Reset Types : Power On Reset (POR), External Reset
(X
The occurrence of a reset is recorded in the Status and
Control Register (CPU_SCR). Bits within this register
record the occurrence of POR and WDR Reset respec-
Table 93:
1.
Status and Control Register (CPU_SCR, Address = Bank 0/1, FFh)
112
Bit 7 : IES Global interrupt enable status from CPU Flag register
0 = Global interrupts disabled
1 = Global interrupts enabled
Bit 6 : Reserved
Bit 5 : WDRS
WDRS is set by the CPU to indicate that a Watchdog Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4 : PORS
PORS is set by the CPU to indicate that a Power On Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)
Bit 3 : Sleep Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending
0 = Normal operation
1 = Sleep
Bit 2 : Reserved
Bit 1 : Reserved
Bit 0 : Stop Set by the user to halt the CPU. The CPU will remain halted until a reset (WDR or POR) has taken place
0 = Normal CPU operation
1 = CPU is halted (not recommended)
Bit Name
res
Read/
Write
Bit #
POR
C = Clear
), and Watchdog Reset (WDR).
Reset
Processor Status and Control Register
IES
R
7
0
Reserved
--
6
0
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
WDRS
R/C
5
0
1
PORS
R/C
4
1
1
tively. The firmware can interrogate these bits to deter-
mine the cause of a reset.
The microcontroller resumes execution from ROM
address 0x0000 after a reset. The internal clocking mode
is active after a reset, until changed by user firmware. In
addition, the Sleep / Watchdog Timer is reset to its mini-
mum interval count.
Important : The CPU clock defaults to divide by 8 mode
at POR to guarantee operation at the low Vcc that might
be present during the supply ramp.
Sleep
RW
3
0
Reserved
2
0
--
Reserved
1
0
--
September 5, 2002
Stop
RW
0
0