Z8F3201AN020EC00TR Zilog, Z8F3201AN020EC00TR Datasheet - Page 179

• Manufacturer Part Number: Z8F3201AN020EC00TR
• Description: IC ENCORE MCU FLASH 32K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3201AN020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F3201AN020EC00T

Table 94. OCD Control Register (OCDCTL)
On-Chip Debugger Control Register Definitions
PS017610-0404
RESET
FIELD
BITS
R/W
OCD Control Register
DBGMODE
R/W
7
0
•
•
The OCD Control register controls the state of the On-Chip Debugger. This register enters
or exits Debug mode and enables the BRK instruction. It can also reset the Z8F640x fam-
ily device.
A “reset and stop” function can be achieved by writing
go” function can be achieved by writing
is in Debug mode, a “run” function can be implemented by writing
DBGMODE—Debug Mode
Setting this bit to 1 causes the Z8F640x family device to enter Debug mode. When in
Debug mode, the eZ8 CPU stops fetching new instructions. Clearing this bit causes the
eZ8 CPU to start running again. This bit is automatically set when a BRK instruction is
decoded and Breakpoints are enabled or when a Watchpoint Debug Break is detected. If
the Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
Z8F640x family device, it cannot be written to 0.
0 = The Z8F640x family device is operating in normal mode.
1 = The Z8F640x family device is in Debug mode.
Write Watchpoint (20H)—The Write Watchpoint command sets and configures the
debug Watchpoint. If the Z8F640x family device is not in Debug mode or the Read
Protect Option Bit is enabled, the WPTCTL bits are all set to zero.
Read Watchpoint (21H)—The Read Watchpoint command reads the current
Watchpoint registers.
DBG <-- 20H
DBG <-- WPTCTL[7:0]
DBG <-- WPTADDR[7:0]
DBG <-- WPTDATA[7:0]
DBG <-- 21H
DBG --> WPTCTL[7:0]
DBG --> WPTADDR[7:0]
DBG --> WPTDATA[7:0]
BRKEN
R/W
6
0
DBGACK
R/W
5
0
R
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
41H
to this register. If the Z8F640x family device
R
3
0
Reserved
81H
R
2
0
to this register. A “reset and
40H
On-Chip Debugger
R
1
0
to this register.
Z8 Encore!
RST
R/W
0
0
®
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