UPSD3234A-40U6 STMicroelectronics, UPSD3234A-40U6 Datasheet - Page 3

• Manufacturer Part Number: UPSD3234A-40U6
• Description: IC FLASH/MCU 64K 80 TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-2372

SUMMARY DESCRIPTION
The uPSD32xx Series combines a fast 8051-
based microcontroller with a flexible memory
structure, programmable logic, and a rich periph-
eral mix including USB, to form an ideal embedded
controller. At its core is an industry-standard 8032
MCU operating up to 40MHz.
A JTAG serial interface is used for In-System Pro-
gramming (ISP) in as little as 10 seconds, perfect
for manufacturing and lab development.
The USB 1.1 low-speed interface has one Control
endpoint and two Interrupt endpoints suitable for
HID class drivers.
The 8032 core is coupled to Programmable Sys-
tem Device (PSD) architecture to optimize the
8032 memory structure, offering two independent
banks of Flash memory that can be placed at vir-
tually any address within 8032 program or data ad-
dress space, and easily paged beyond 64K bytes
using on-chip programmable decode logic.
Figure 2. Block Diagram
P3.0:7
P1.0:7
P4.0:7
USB+,
USB–
Interrupts
(3) 16-bit
Counters
External
Timer/
(2)
(8) GPIO, Port 3
(8) GPIO, Port 1
(8) GPIO, Port 4
(5) 8-bit PWM
(4) 8-bit ADC
USB v1.1
UART1
UART0
I
2
C
MCU
8032
Core
uPSD32xx
Dual Flash memory banks provide a robust solu-
tion for remote product updates in the field through
In-Application Programming (IAP). Dual Flash
banks also support EEPROM emulation, eliminat-
ing the need for external EEPROM chips.
General purpose programmable logic (PLD) is in-
cluded to build an endless variety of glue-logic,
saving external logic devices. The PLD is config-
ured using the software development tool, PSD-
soft
www.st.com/psm, at no charge.
The uPSD32xx also includes supervisor functions
such as a programmable watchdog timer and low-
voltage reset.
Programmable
Programmable
16 Macrocells
Decode and
Page Logic
Watchdog and Low-Voltage Reset
Purpose
V
General
8032 Address/Data/Control Bus
Logic,
CC
, V
Express,
(80-pin device only)
DD
, GND, Reset, Crystal In
JTAG ISP
Supervisor:
2K, 8K, or 32K Bytes
2nd Flash Memory:
1st Flash Memory:
16K or 32K Bytes
(8) GPIO, Port B
(2) GPIO, Port D
(4) GPIO, Port C
(8) GPIO, Port A
or 256K Bytes
(80-pin only)
64K, 128K,
available
SRAM:
from
the
uPSD32xx
Dedicated
PA0:7
PB0:7
PD1:2
PC0:7
AI10401
web
MCU
Bus
Pins
3/8
at