ATTINY167-15MD Atmel, ATTINY167-15MD Datasheet - Page 17
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ATTINY167-15MD
Manufacturer Part Number
ATTINY167-15MD
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MD
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.2.1
3.3
7728G–AVR–06/10
EEPROM Data Memory
Data Memory Access Times
Figure 3-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 3-3.
The ATtiny87/167 contains EEPROM memory (see “E2 size” in
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The
access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control
Register.
Section 21. “Memory Programming” on page 225
programming in SPI or Parallel Programming mode.
Address
clk
Data
Data
Data Memory Map
On-chip Data SRAM Access Cycles
WR
CPU
RD
Compute Address
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
Data Memory
(ISRAM size)
32 Registers
T1
Memory Access Instruction
Address valid
ISRAM end
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
ISRAM start
T2
contains a detailed description on EEPROM
CPU
cycles as described in
ATtiny87/ATtiny167
Next Instruction
Table 3-1 on page
T3
Figure
3-3.
15). It is
17
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