AT91SAM7X256-AU-999 Atmel, AT91SAM7X256-AU-999 Datasheet - Page 28
![IC ARM7 MCU 256K FLASH 100-LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
AT91SAM7X256-AU-999
Manufacturer Part Number
AT91SAM7X256-AU-999
Description
IC ARM7 MCU 256K FLASH 100-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X256B-CU.pdf
(45 pages)
Specifications of AT91SAM7X256-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7X256-AU-999TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9.3
9.4
28
Power Management Controller
Advanced Interrupt Controller
AT91SAM7X512/256/128 Preliminary
The Power Management Controller uses the Clock Generator outputs to provide:
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Figure 9-3.
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK
• all the peripheral clocks, independently controllable
• four programmable clock outputs
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and vectored interrupt sources
• 8-level Priority Controller
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
– Drives the normal interrupt nIRQ of the processor
– Handles priority of the interrupt sources
sources
Power Management Controller Block Diagram
MAINCK
PLLCK
MAINCK
SLCK
PLLCK
SLCK
PLLCK
Master Clock Controller
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
USB Clock Controller
/1,/2,/4,...,/64
ON/OFF
Divider
/1,/2,/4
Prescaler
Processor
Controller
Idle Mode
Clock Controller
Clock
Peripherals
ON/OFF
int
UDPCK
PCK
MCK
periph_clk[2..18]
pck[0..3]
6120FS–ATARM–17-Feb-09