ATTINY44V-10MU Atmel, ATTINY44V-10MU Datasheet - Page 165
![IC MCU AVR 4K FLASH 10MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY44V-10MU
Manufacturer Part Number
ATTINY44V-10MU
Description
IC MCU AVR 4K FLASH 10MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
20MLF
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY44V-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 165 of 238
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19.5.2
Table 19-12. Serial Programming Instruction Set
8006K–AVR–10/10
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Extended Fuse Bits
Read Calibration Byte
Serial Programming Instruction set
(1)
Table 19-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
The instruction set is described in
Symbol
t
t
t
t
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
WD_FLASH
WD_EEPROM
WD_ERASE
WD_FUSE
next page (See
file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
power off.
Table 19-11 on page
Byte 1
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
$50
$38
Table 19-12
adr MSB
adr MSB
adr MSB
adr MSB
165). In a chip erased device, no 0xFF in the data
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
and
Instruction Format
Figure 19-2 on page
Minimum Wait Delay
Extended adr
4.5 ms
4.0 ms
9.0 ms
4.5 ms
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
$00
$00
$00
$00
$00
$00
$00
$00
ATtiny24/44/84
166.
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
Byte4
$00
$00
$00
165
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