ATTINY44V-10MU Atmel, ATTINY44V-10MU Datasheet - Page 161
![IC MCU AVR 4K FLASH 10MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY44V-10MU
Manufacturer Part Number
ATTINY44V-10MU
Description
IC MCU AVR 4K FLASH 10MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
20MLF
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY44V-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.2.1
19.3
8006K–AVR–10/10
Device Signature Imprint Table
Latching of Fuses
Table 19-5.
Notes:
Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro-
grammed before lock bits. The status of fuse bits is not affected by chip erase.
Fuse bits can also be read by device firmware. See section
Data from Software” on page
Fuse values are latched when the device enters programming mode and changes to fuse values
have no effect until the part leaves programming mode. This does not apply to the EESAVE
Fuse which will take effect once it is programmed. Fuses are also latched on power-up.
The device signature imprint table is a dedicated memory area used for storing miscellaneous
device information, such as the device signature and oscillator calibration data. Most of this
memory segment is reserved for internal use, as outlined in
Table 19-6.
Notes:
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
Address
0x00
0x01
0x02
0x03
0x04
0x05 ... 0x2A
(3)
(3)
1. See
2. Allows system clock to be output on pin. See
3. The default value results in maximum start-up time for the default clock source. See
4. The default setting results in internal RC Oscillator @ 8.0 MHz. See
1. See section “Signature Bytes” for more information.
2. See section “Calibration Byte” for more information.
(2)
(1)
(4)
(4)
(4)
(4)
on page 27
details.
Fuse Low Byte
Contents of Device Signature Imprint Table.
“System Clock Prescaler” on page 30
High Byte
Signature byte 0
Calibration data for internal oscillator
Signature byte 1
Reserved for internal use
Signature byte 2
Reserved for internal use
for details.
Bit No
155.
7
6
5
4
3
2
1
0
(1)
(1)
(1)
Description
Divide clock by 8
Clock Output Enable
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
(2)
“Clock Output Buffer” on page 30
“Reading Lock, Fuse and Signature
Table
19-6.
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
ATtiny24/44/84
Table 6-4 on page 27
for details.
Table 6-5
161
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