AT89C5131A-TISIL Atmel, AT89C5131A-TISIL Datasheet - Page 137
AT89C5131A-TISIL
Manufacturer Part Number
AT89C5131A-TISIL
Description
IC 8051 MCU FLASH 32K USB 28SOIC
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5131A-TISIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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4338F–USB–08/07
Table 93. USBINT Register
USBINT (S:BDh)
USB Global Interrupt Register
Reset Value = 00h
Bit Number
7-6
7
-
5
4
3
2
1
0
Mnemonic Description
WUPCPU
EORINT
SOFINT
SPINT
Bit
6
-
-
-
-
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in Table 94 on page 138.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit will be cleared by software (USB clocks must be enabled before).
End Of Reset Interrupt
This bit is set by hardware when a End Of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set (see Figure 94 on
page 138).
This bit will be cleared by software.
Start of Frame Interrupt
This bit is set by hardware when an USB Start of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set (see Table 94 on
page 138).
This bit will be cleared by software.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in see Table 94 on page 138.
This bit will be cleared by software BEFORE any other USB operation to re-
activate the macro.
WUPCPU
5
EORINT
4
SOFINT
3
2
-
1
-
SPINT
0
137
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