AT89C5131A-PUTIM Atmel, AT89C5131A-PUTIM Datasheet - Page 99
AT89C5131A-PUTIM
Manufacturer Part Number
AT89C5131A-PUTIM
Description
IC 8051 MCU FLASH 32K USB 32QFN
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5131A-PUTIM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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19.3.5
19.3.5.1
4337K–USB–04/08
Registers
Serial Peripheral Control Register (SPCON)
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent
with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt
requests.
Figure 19-7 gives a logical view of the above statements.
Figure 19-7. SPI Interrupt Requests Generation
There are three registers in the module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
Table 19-3 describes this register and explains the use of each bit.
Table 19-3.
• The Serial Peripheral Control Register does the following:
Number
SPR2
Bit
7
6
5
4
3
7
– Selects one of the Master clock rates
– Configure the SPI module as Master or Slave
– Selects serial clock polarity and phase
– Enables the SPI module
– Frees the SS pin for a general-purpose
Bit Mnemonic
SPCON Register
SSDIS
MSTR
SPEN
CPOL
SPEN
SPR2
SPIF
MODF
SSDIS
6
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no
effect if CPHA = “0”.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to “0” in idle state.
Set to have the SCK set to “1” in idle state.
SSDIS
5
SPI Transmitter
CPU Interrupt Request
SPI Receiver/Error
CPU Interrupt Request
MSTR
4
CPOL
3
AT89C5130A/31A-M
CPU Interrupt Request
CPHA
2
SPI
SPR1
1
SPR0
0
99
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