DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 17

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

32. Page 17-46, Section 17.16 A/D Sampling
The entire Section 17.16 should be replaced with the
following text and figures:
33. Page 18-12, Section 18.7 Selecting the
 2004 Microchip Technology Inc.
On page 18-12, Section 18.7 Selecting the A/D
Conversion Clock, paragraph 3 should be
replaced with the following:
Also remove Table 18-1: Typical T
Operating Frequencies.
Requirements
A/D Conversion Clock
The analog input model of the 10-bit A/D converter is shown in Figure 17-21. The total sampling
time for the A/D is a function of the internal amplifier settling time and the holding capacitor
charge time.
For the A/D converter to meet its specified accuracy, the charge holding capacitor (C
be allowed to fully charge to the voltage level on the analog input pin. The source impedance
(R
combine to directly affect the time required to charge the capacitor C
ance of the analog sources must therefore be small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy
of the A/D converter, the maximum recommended source impedance, R
analog input channel is selected (changed), this sampling function must be completed prior to
starting the conversion. The internal holding capacitor will be in a discharged state prior to each
sample operation.
At least 1 T
details, see the device electrical specifications.
Figure 17-21:
For correct A/D conversions, the A/D conversion clock (T
minimum T
Note: C
S
), the interconnect impedance (R
Legend: C
VA
PIN
Rs
AD
AD
value depends on device package and is not tested. Effect of C
time period should be allowed between conversions for the sample time. For more
time of 667 nsec (for V
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
10-bit A/D Converter Analog Input Model
AD
PIN
dsPIC30F Family Reference Manual
vs. Device
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
V
DD
V
V
T
T
DD
= 0.6V
= 0.6V
IC
), and the internal sampling switch (R
= 5V).
R
I leakage
IC
500 nA
250
AD
Sampling
Switch
) must be selected to ensure a
R
SS
HOLD
PIN
R
negligible if Rs
. The combined imped-
SS
V
SS
C
= DAC capacitance
= 4.4 pF
S
HOLD
, is 5 k . After the
3 k
DS80169E-page 17
SS
) impedance
HOLD
5 k .
) must