DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

dsPIC30F Family Reference Manual
14. Page 5-11, Section 5.4.2.2 Erasing a Row
DS80169E-page 10
On page 5-11, Section 5.4.2.2 Erasing a Row of
Program Memory should be replaced with the
following:
of Program Memory
5.4.2.2
Erasing a Row of Program Memory
The following is a code sequence that can be used to erase a row (32 instructions) of program
memory. The NVMCON register is configured to erase one row of program memory. The
NVMADRU and NVMADR registers are loaded with the address of the row to be erased. The
program memory must be erased at ‘even’ row boundaries. Therefore, the 6 LSbits of the value
written to the NVMADR register have no effect when a row is erased.
The erase operation is initiated by writing a special unlock, or key sequence to the NVMKEY
register before setting the WR control bit (NVMCON<15>). The unlock sequence needs to be
executed in the exact order shown without interruption. Therefore, interrupts should be disabled
prior to writing the sequence.
Two NOP instructions should be inserted in the code at the point where the CPU will resume
operation. Finally, interrupts can be enabled (if required).
; Setup NVMCON to erase one row of Flash program memory
; Setup address pointer to row to be ERASED
; Disable interrupts, if enabled
; Write the KEY sequence
; Start the erase operation
; Insert two NOPs after the erase cycle (required)
; Re-enable interrupts, if needed
Note:
MOV
MOV
MOV
MOV
MOV
MOV
PUSH
MOV
IOR
MOV
MOV W0,
MOV #0xAA, W0
MOV W0,
BSET
NOP
NOP
POP
When erasing a row of program memory, the user writes the upper 8 bits of the erase
address directly to the NVMADRU and NVMADR registers. Together, the contents
of the NVMADRU and NVMADR registers form the complete address of the program
memory row to be erased.
The NVMADRU and NVMADR registers specify the address for all Flash erase and
program operations. However, these two registers do not have to be directly written
by the user for Flash program operations. This is because the table write instructions
used to write the program memory data automatically transfers the TBLPAG register
contents and the table write address into the NVMADRU and NVMADR registers.
The above code example could be modified to perform a ‘dummy’ table write
operation to capture the program memory erase address.
#0x4041,W0
W0
#tblpage(PROG_ADDR),W0
W0
#tbloffset(PROG_ADDR),W0
W0,NVMADR
SR
#0x00E0,W0
SR
NVMCON,#WR
SR
,
,
NVMCON
NVMADRU
#0x55,W0
NVMKEY
NVMKEY
 2004 Microchip Technology Inc.