ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 215
ATMEGA165-16MI
Manufacturer Part Number
ATMEGA165-16MI
Description
IC AVR MCU 16K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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BYPASS; 0xF
Boundary-scan Related
Register in I/O Memory
MCU Control Register –
MCUCR
2573G–AVR–07/09
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling
or enabling of the JTAG interface, a timed sequence must be followed when changing
this bit: The application software must write this bit to the desired value twice within four
cycles to change its value. Note that this bit must not be altered when using the On-chip
Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be
set to one. The reason for this is to avoid static current at the TDO pin in the JTAG
interface.
Bit
Read/Write
Initial Value
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
R/W
JTD
7
0
R
6
–
0
R
5
–
0
PUD
R/W
4
0
R
3
–
0
R
2
–
0
ATmega165/V
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
215
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