ATMEGA165-16AU Atmel, ATMEGA165-16AU Datasheet - Page 49

• Manufacturer Part Number: ATMEGA165-16AU
• Description: IC AVR MCU 16K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Moving Interrupts Between
Application and Boot Space
MCU Control Register –
MCUCR
2573G–AVR–07/09
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typ-
ical and general program setup for the Reset and Interrupt Vector Addresses is:
The General Interrupt Control Register controls the placement of the Interrupt Vector
table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-Programming” on page 232 for details. To avoid unin-
tentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
Bit
Read/Write
Initial Value
Address
;
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C2C
;
0x1C2E
0x1C2F
0x1C30
0x1C31
0x1C32
0x1C33
1.Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.Within four cycles, write the desired value to IVSEL while writing a zero to
IVCE.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-
gramed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-Programming” on page 232
for details on Boot Lock bits.
Labels Code
RESET: ldi
R/W
JTD
7
0
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
R
6
–
0
RESET
EXT_INT0
PCINT0
...
SPM_RDY
r16,high(RAMEND) ; Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
R
5
–
0
PUD
R/W
4
0
Comments
; Reset handler
; IRQ0 Handler
; PCINT0 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
R
3
–
0
R
2
–
0
ATmega165/V
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
49