ATAM893T-TKQ Atmel, ATAM893T-TKQ Datasheet - Page 47

• Manufacturer Part Number: ATAM893T-TKQ
• Description: IC MON TIRE-PRESS ATARX9X SER
• Manufacturer: Atmel
• Series: MARC4r

Specifications of ATAM893T-TKQ

• Core Processor: MARC4
• Core Size: 4-Bit
• Speed: 4MHz
• Connectivity: SSI (2-Wire, 3 Wire)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 16
• Ram Size: 256 x 4
• Voltage - Supply (vcc/vdd): 1.8 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

5.3.3
5.3.3.1
Figure 5-24. Timer 3
4680C–4BMCU–01/05
T3I
Timer 3
T1OUT
SYSCL
POUT
Features
T3EX
T3CS
CL3
RES
Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The
timer can be used as event counter, timer and signal generator. Its output can be programmed
as modulator and demodulator for the serial interface. The two compare registers enable various
modes of signal generation, modulation and demodulation. The counter can be driven by inter-
nal and external clock sources. For external clock sources, it has a programmable edge-
sensitive input which can be used as counter input, capture signal input or trigger input. This
timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core
capture register while it is running. In capture mode, the counter value can be captured by a pro-
grammable capture event from the Timer 3 input or Timer 2 output.
Compare 3/1
• Two Compare Registers
• Capture Register
• Edge Sensitive Input with Zero Cross Detection Capability
• Trigger and Single Action Modes
• Output Control Modes
• Automatic Modulation and Demodulation Modes
• FSK Modulation
• Pulse width Modulation (PWM)
• Manchester Demodulation Together with SSI
• Bi-phase Demodulation Together with SSI
• Pulse-width Demodulation Together with SSI
T3CO1
sleep and OSC-Stop
8-bit Counter 3
T3CP
Compare 3/2
T3CO2
CP3
I/O-bus
I/O-bus
yes), this timer input is stopped too. The counter is readable via its
T3CM1
T3C
Control
T3CM2
T3ST
TOG2
Timer 2
T3M
Control
T3EX
CM31
INT5
RES
SO
T3I
TOG3
M2
SSI
Modulator 3
Demodu-
ATAM893-D
lator 3
SCI
SI
SSI
T3O
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