ATMEGA8L-8PJ Atmel, ATMEGA8L-8PJ Datasheet - Page 121
ATMEGA8L-8PJ
Manufacturer Part Number
ATMEGA8L-8PJ
Description
IC MCU AVR 8K 5V 8MHZ 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8L-8PJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Serial
Peripheral
Interface – SPI
2486Z–AVR–02/11
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes
the following features:
•
•
•
•
•
•
•
•
Figure 57. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
122. The system consists of two Shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted
from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the
Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
1. Refer to
DIVIDER
“Pin Configurations” on page
(1)
2, and
Table 22 on page 58
for SPI pin placement
ATmega8(L)
Figure 58 on page
121
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