ATMEGA8515L-8JJ Atmel, ATMEGA8515L-8JJ Datasheet - Page 131
![IC MCU AVR 8K 5V 8MHZ 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8515L-8JJ
Manufacturer Part Number
ATMEGA8515L-8JJ
Description
IC MCU AVR 8K 5V 8MHZ 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515L-8JJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 131 of 257
- Download datasheet (2Mb)
SS Pin Functionality
Slave Mode
Master Mode
SPI Control Register – SPCR
2512K–AVR–01/10
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When
SS is held low, the SPI is activated, and MISO becomes an output if configured so by
the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the
SPI is passive, which means that it will not receive incoming data. Note that the SPI
logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the Slave bit counter syn-
chronous with the master clock generator. When the SS pin is driven high, the SPI Slave
will immediately reset the send and receive logic, and drop any partially received data in
the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine
the direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the
SPI system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If
the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master
with the SS pin defined as an input, the SPI system interprets this as another Master
selecting the SPI as a Slave and starting to send data to it. To avoid bus contention, the
SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. If the MSTR bit has been cleared by a Slave Select, it must be set by the user to
re-enable SPI Master mode.
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable
any SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
Bit
Read/Write
Initial Value
result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
SREG is set, the interrupt routine will be executed.
SPIE
R/W
7
0
SPE
R/W
6
0
DORD
R/W
5
0
MSTR
R/W
4
0
CPOL
R/W
3
0
CPHA
R/W
2
0
ATmega8515(L)
SPR1
R/W
1
0
SPR0
R/W
0
0
SPCR
131
Related parts for ATMEGA8515L-8JJ
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![ATMEGA128RFA1-ZU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA328P-20PU](/images/manufacturer_photos/0/0/78/atmel_tmb.jpg)
Part Number:
Description:
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAV-10PU](/photos/14/18/141872/atmega64rzav-10pu_tmb.jpg)
Part Number:
Description:
MCU ATMEGA644/AT86RF230 40-DIP
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAPV-10MU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAPV-10AU](/photos/6/70/67042/313-44-tqfp_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZAV-8AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA1281/AT86RF230 64-TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZBV-8AU](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA1280/AT86RF230 100TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZBV-8CU](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA1280/AT86RF100-TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA256RZBV-8CU](/photos/6/89/68968/313-100-cbga_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA2560V/AT86RF230-ZU
Manufacturer:
Atmel
Datasheet:
![ATMEGA256RZAV-8AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer:
Atmel
Datasheet:
![U641B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
![U4082B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
![U4089B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
![U4255BM-M](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet: