ATMEGA48-20MJ Atmel, ATMEGA48-20MJ Datasheet - Page 151
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ATMEGA48-20MJ
Manufacturer Part Number
ATMEGA48-20MJ
Description
IC AVR MCU 4K 5V 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48-20MJ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA48-24MJ
ATMEGA48-24MJ
ATMEGA48-24MJ
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17.10 Timer/Counter Prescaler
2545S–AVR–07/10
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare pin is changed on the timer clock and is not synchronized to the processor
clock.
Figure 17-12. Prescaler for Timer/Counter2
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP.
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock
(clk
until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-
save mode is essentially unpredictable, as it depends on the wake-up time. The recommended
procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
I/O
PSRASY
) again becomes active, TCNT2 will read as the previous value (before entering sleep)
TOSC1
clk
CS20
CS21
CS22
AS2
I/O
clk
T2S
Clear
TIMER/COUNTER2 CLOCK SOURCE
0
10-BIT T/C PRESCALER
clk
T2
ATmega48/88/168
151
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