AT89C5131A-PLTIL Atmel, AT89C5131A-PLTIL Datasheet - Page 91

• Manufacturer Part Number: AT89C5131A-PLTIL
• Description: IC 8051 MCU FLASH 32K USB 48QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-PLTIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89C5131-PLTIL

Baud Rate
4338F–USB–08/07
pins (Figure 42). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Section “Error Conditions”, page 95).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
Notes:
In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 72 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 72. SPI Master Baud Rate Selection
SPR2
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
0
0
0
0
1
1
1
1
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in
this mode, the SS is used to start the transmission.
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
(1)
.
F
F
F
F
Clock Rate
F
F
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
Don’t Use
CLK PERIPH
CLK PERIPH
Don’t Use
/128
/16
/32
/64
/4
/8
Baud Rate Divisor (BD)
No BRG
No BRG
128
16
32
64
4
8
(2)
This
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