AT89C5131A-PLTIL Atmel, AT89C5131A-PLTIL Datasheet - Page 160
AT89C5131A-PLTIL
Manufacturer Part Number
AT89C5131A-PLTIL
Description
IC 8051 MCU FLASH 32K USB 48QFN
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5131A-PLTIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
AT89C5131-PLTIL
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Notes:
160
Symbol
V
PFDM
1. Operating I
2. Idle I
3. Power-down I
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.
6. Under steady state (non-transient) conditions, I
AT89C5131A-L
V
V
78.).
0.5V; XTAL2 N.C; Port 0 = V
ure 80.). In addition, the WDT must be inactive and the POF flag must be set.
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
Maximum I
Maximum I
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
If I
than the listed test conditions.
Parameter
Power Fail Low Level Threshold
Power fail hysteresis V
SS
IH
OL
= V
+ 0.5V,
CC
exceeds the test condition, V
CC
is measured with all output pins disconnected; XTAL1 driven with T
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
OL
OL
CC
CC
per port pin: 10 mA
per 8-bit port:
is measured with all output pins disconnected; XTAL1 driven with T
OL
is measured with all output pins disconnected; EA = V
OL
for all output pins: 71 mA
PFDP
peak 0.6V. A Schmitt Trigger use is not necessary.
- V
Figure 78. I
PFDM
CC
; EA = RST = V
OL
CLOCK
SIGNAL
may exceed the related specification. Pins are not guaranteed to sink current greater
CC
(NC)
Test Condition, Active Mode
SS
OL
(see Figure 79).
must be externally limited as follows:
Min
0.15
2.2
RST
XTAL2
XTAL1
V
CC
SS
. I
CC
V
EA
CC
would be slightly higher if a crystal oscillator used (see Figure
I
P0
CC
Typ
V
CC
V
(5)
CC
CC
, PORT 0 = V
CLCH
, T
Max
All other pins are disconnected.
CLCH
CHCL
, T
CC
= 5 ns, V
CHCL
; XTAL2 NC.; RST = V
Unit
= 5 ns (see Figure 81.), V
V
V
IL
= V
Test Conditions
OLS
SS
of ALE and Ports 1
+ 0.5V, V
4338F–USB–08/07
SS
IH
(see Fig-
= V
CC
IL
=
-
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