AT89C5122D-RDVIM Atmel, AT89C5122D-RDVIM Datasheet - Page 100
![IC 8051 MCU W/SMART CARD 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDVIM
Manufacturer Part Number
AT89C5122D-RDVIM
Description
IC 8051 MCU W/SMART CARD 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-RDVIM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122D-RDTIM
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Read/Write Data FIFO
Read Data FIFO
Write Data FIFO
100
AT83R5122, AT8xC5122/23
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the
FIFO and the byte counter of the endpoint is updated (UBYCTX register). The firmware
has to store the endpoint byte counter before any access to the endpoint FIFO. The byte
counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and
read the UEPDATX register. This action automatically decreases the corresponding
address vector, and the next data is then available in the UEPDATX register.
The write access for each IN endpoint is performed using the UEPDATX register.
To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEP-
NUM and write into the UEPDATX register. The corresponding address vector is
automatically increased, and another write can be carried out.
Warning 1: The byte counter is not updated.
Warning 2: Do not write more bytes than supported by the corresponding endpoint.
Figure 53. Endpoint FIFO Configuration
138H
F8H
B8H
78H
38H
30H
28H
20H
00H
Endpoint 6 - bank 1
Endpoint 6 - bank 0
Endpoint 5 - bank 0
Endpoint 4 - bank 0
Endpoint 3 - bank 0
Endpoint 2 - bank 0
Endpoint 1 - bank 0
Endpoint 0 - bank 0
2 x 64 Bytes
8 Bytes
8 Bytes
8 Bytes
32 Bytes
64 Bytes
64 Bytes
4202F–SCR–07/2008
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