PIC18F2515-E/SP Microchip Technology, PIC18F2515-E/SP Datasheet - Page 5

• Manufacturer Part Number: PIC18F2515-E/SP
• Description: IC MCU FLASH 24KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2515-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17. Module: EUSART
18. Module: EUSART
19. Module: Timer1/Timer3
© 2007 Microchip Technology Inc.
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted
transmission) is not written immediately follow-
ing the setting of TXIF. This is because any
write to the TXSTA register results in a reset of
the baud rate timer which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTA register is set), the
second byte may be corrupted if it is written into
TXREG immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREG.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is configured for the
external clock source and the CCPxCON register
is configured with 0x0B (Compare mode, trigger
special event), the timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer registers upon
detection of the compare match condition —
TMRxL and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
a
transmission
if
the
TX9D
is
bit
not
(for
in
the
PIC18F2515/2610/4515/4610
progress
next
20. Module: Timer1/Timer3
21. Module: Timer1/Timer3
22. Module: MSSP
When Timer1 or Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 T
be skipped.
Work around
Avoid using an external clock with a period
(1/frequency) between 1 and 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
were written.
Work around
Two work arounds are available: 1) Stop
Timer1/Timer3 before writing the TMR1H/TMR3H
registers; 2) Write TMR1L/TMR3L immediately
after writing TMR1H/TMR3H.
Date Codes that pertain to this issue:
All engineering and production devices.
I
bit should be set) only when the system is idle
(i.e., when ACKEN, RCEN, PEN, RSEN and SEN
all equal zero). It should not be possible to set the
RCEN bit when the system is not idle, however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become idle before setting the
RCEN bit. This requires a check for the following bits
to be clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C Receive mode should be enabled (i.e., RCEN
CY
, interrupts will occasionally
CY
DS80199E-page 5
.