DSPIC30F5011T-20I/PT Microchip Technology, DSPIC30F5011T-20I/PT Datasheet
DSPIC30F5011T-20I/PT
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DSPIC30F5011T-20I/PT Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance Digital Signal Controllers Preliminary DS70116E ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructins are single cycle - Multiply-Accumulate (MAC) operation • Single cycle ±16 shift 2004 Microchip Technology Inc. dsPIC30F5011/5013 Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16- bit timers into 32-bit timer modules • ...
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... Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption Output SRAM EEPROM Timer Input Comp/Std Bytes Bytes 16-bit Cap PWM 4096 1024 4096 1024 Preliminary Codec A/D 12-bit Interface 100 Ksps 2 AC’97 AC’97 2004 Microchip Technology Inc. ...
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... SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: For descriptions of individual pins, see Section 1.0. 2004 Microchip Technology Inc. dsPIC30F5011/5013 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F5011 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 ...
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... AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: For descriptions of individual pins, see Section 1.0. DS70116E-page dsPIC30F5013 Preliminary EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 5 ...
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... NOTES: DS70116E-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). 2004 Microchip Technology Inc. dsPIC30F5011/5013 This document contains specific information for the dsPIC30F5011/5013 Digital Signal Controller (DSC) devices ...
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... OSC2/CLKO/RC15 PORTC EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 PORTD C1RX/RF0 C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15 PORTG 2004 Microchip Technology Inc. ...
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... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low Voltage Detect CAN1, 12-bit ADC CAN2 Timers 2004 Microchip Technology Inc. dsPIC30F5011/5013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (2 Kbytes) (2 Kbytes) 16 Address Address Latch Latch 16 16 ...
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... Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. ST Compare Fault A input (for Compare channels and 4). ST Compare Fault B input (for Compare channels and 8). — Compare outputs 1 through 8. Analog = Analog input O = Output P = Power Preliminary Description 2004 Microchip Technology Inc. ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2004 Microchip Technology Inc. dsPIC30F5011/5013 Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes ...
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... NOTES: DS70116E-page 12 Preliminary 2004 Microchip Technology Inc. ...
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... Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. 2004 Microchip Technology Inc. dsPIC30F5011/5013 There are two methods of accessing data stored in program memory: • ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary 2004 Microchip Technology Inc. ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH 2004 Microchip Technology Inc. dsPIC30F5011/5013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...
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... The REPEAT loop count must be setup for 18 iterations of the DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function Preliminary 2004 Microchip Technology Inc. ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC 2004 Microchip Technology Inc. dsPIC30F5011/5013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70116E-page 18 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill 2004 Microchip Technology Inc. ...
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... B) as its pre- accumulation source and post-accumulation destina- tion. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2.4.2.1 Adder/Subtracter, Overflow and Saturation ...
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... Section 2.4.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary 2004 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70116E-page 22 Preliminary 2004 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. 2004 Microchip Technology Inc. dsPIC30F5011/5013 FIGURE 3-1: PROGRAM SPACE MEMORY MAP ...
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... DS70116E-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA PSVPAG Reg 8 bits 15 bits EA TBLPAG Reg 8 bits 16 bits 24-bit EA Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select 2004 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) 2004 Microchip Technology Inc. dsPIC30F5011/5013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; ...
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... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. Preliminary 8 0 2004 Microchip Technology Inc. ...
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... DSP instruc- tions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Program Space 0x0000 (1) PSVPAG ...
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... The data space memory map is shown in Figure 3-6. LS Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 Y Data RAM (Y) 0x17FE 0x1800 0x1FFE 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space 2004 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W 2004 Microchip Technology Inc. dsPIC30F5011/5013 SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops (Read) ...
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... FIGURE 3-8: MS Byte 15 0001 Byte1 0x0000 Byte3 0003 0x0000 Byte5 0005 0x0000 Preliminary backward compatibility with DATA ALIGNMENT LS Byte 0000 Byte 0 Byte 2 0002 Byte 4 0004 2004 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. 2004 Microchip Technology Inc. dsPIC30F5011/5013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> ...
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... DS70116E-page 32 Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 33 ...
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... NOTES: DS70116E-page 34 Preliminary 2004 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 2004 Microchip Technology Inc. dsPIC30F5011/5013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buff- ers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Preliminary 2004 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2004 Microchip Technology Inc. dsPIC30F5011/5013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers ...
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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Preliminary N bytes, addressing and bit-reversed 2004 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 2048 1024 512 256 128 2004 Microchip Technology Inc. dsPIC30F5011/5013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary A0 Decimal ...
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... NOTES: DS70116E-page 40 Preliminary 2004 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit ...
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... INT4 - External Interrupt Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI - Codec Transfer Done 42 50 LVD - Low Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Preliminary 2004 Microchip Technology Inc. Interrupt Source 2 C Slave Interrupt 2 C Master Interrupt ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. 2004 Microchip Technology Inc. dsPIC30F5011/5013 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...
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... Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector Preliminary 2004 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 — — — 0x00007E 0x000080 0x000082 0x000084 0x000094 — ...
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... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. 2004 Microchip Technology Inc. dsPIC30F5011/5013 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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... DS70116E-page 46 Preliminary 2004 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select 2004 Microchip Technology Inc. dsPIC30F5011/5013 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 for DD further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Preliminary 2004 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP 2004 Microchip Technology Inc. dsPIC30F5011/5013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 51 ...
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... NOTES: DS70116E-page 52 Preliminary 2004 Microchip Technology Inc. ...
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... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Preliminary 2004 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete 2004 Microchip Technology Inc. dsPIC30F5011/5013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority <7 for ; next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle Preliminary 2004 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. 2004 Microchip Technology Inc. dsPIC30F5011/5013 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70116E-page 58 Preliminary 2004 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port 2004 Microchip Technology Inc. dsPIC30F5011/5013 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... NOP will be EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISB NOP btss PORTB, #13 Preliminary I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; additional instruction cycle ; bit test RB13 and skip if set 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 61 ...
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... DS70116E-page 62 Preliminary 2004 Microchip Technology Inc. ...
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... CN7PUE CN6PUE CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE Legend uninitialized bit Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Bit 13 Bit 12 Bit 11 Bit 10 CN13IE CN12IE CN11IE CN10IE — ...
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... NOTES: DS70116E-page 64 Preliminary 2004 Microchip Technology Inc. ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI 2004 Microchip Technology Inc. dsPIC30F5011/5013 These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K Preliminary SOSCI dsPIC30FXXXX SOSCO 2004 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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... DS70116E-page 68 Preliminary 2004 Microchip Technology Inc. ...
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... Interrupt on a 32-bit period register match These Operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. 2004 Microchip Technology Inc. dsPIC30F5011/5013 For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer. ...
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... Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70116E-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 Q D TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Preliminary Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK 2004 Microchip Technology Inc. dsPIC30F5011/5013 PR2 Comparator x 16 TMR2 Q D TGATE Q CK TON 1 x Gate Sync PR3 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 73 ...
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... NOTES: DS70116E-page 74 Preliminary 2004 Microchip Technology Inc. ...
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... T4CK Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. 2004 Microchip Technology Inc. dsPIC30F5011/5013 • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral ...
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... TCS = 0, TGATE = 1 (gated time accumulation) DS70116E-page 76 PR4 Comparator x 16 TMR4 Q D TGATE Q CK TON 1 x Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Preliminary Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 77 ...
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... NOTES: DS70116E-page 78 Preliminary 2004 Microchip Technology Inc. ...
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... ICBNE, ICOV ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. 2004 Microchip Technology Inc. dsPIC30F5011/5013 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. Preliminary 2004 Microchip Technology Inc. module is defined as ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 81 ...
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... NOTES: DS70116E-page 82 Preliminary 2004 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. 2004 Microchip Technology Inc. dsPIC30F5011/5013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Preliminary 2004 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. 2004 Microchip Technology Inc. dsPIC30F5011/5013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70116E-page 86 Preliminary 2004 Microchip Technology Inc. ...
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... Note: Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF. 2004 Microchip Technology Inc. dsPIC30F5011/5013 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit ...
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... Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Preliminary Secondary Primary CY F Prescaler Prescaler 1:1 – 1 16, 64 SPI™ Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 2004 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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... DS70116E-page 90 Preliminary 2004 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 2004 Microchip Technology Inc. dsPIC30F5011/5013 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
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... Addr_Match Match Detect I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter CY F Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read 2004 Microchip Technology Inc. ...
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... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. 2004 Microchip Technology Inc. dsPIC30F5011/5013 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
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... SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Preliminary 2004 Microchip Technology Inc. 2 CRCV ...
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... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2 15. Master Operation The master device generates all of the serial clock ...
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... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 97 ...
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... NOTES: DS70116E-page 98 Preliminary 2004 Microchip Technology Inc. ...
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... Internal Data Bus UTXBRK Data UxTX Parity Note 2004 Microchip Technology Inc. dsPIC30F5011/5013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
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... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Preliminary Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF 2004 Microchip Technology Inc. ...
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... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). 2004 Microchip Technology Inc. dsPIC30F5011/5013 16.3 Transmitting Data 16.3.1 ...
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... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Preliminary 2004 Microchip Technology Inc. RXB) X ...
Page 105
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. 2004 Microchip Technology Inc. dsPIC30F5011/5013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 106
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Preliminary 2004 Microchip Technology Inc. ...
Page 107
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 105 ...
Page 108
... NOTES: DS70116E-page 106 Preliminary 2004 Microchip Technology Inc. ...
Page 109
... Programmable link to Input Capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • Low power Sleep and Idle mode 2004 Microchip Technology Inc. dsPIC30F5011/5013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 110
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX 2004 Microchip Technology Inc. ...
Page 111
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. 2004 Microchip Technology Inc. dsPIC30F5011/5013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 112
... End of Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. Preliminary 2004 Microchip Technology Inc. ...
Page 113
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 114
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 µsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Preliminary Q . Also, by definition, Sync 2004 Microchip Technology Inc. ...
Page 115
... SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg 2004 Microchip Technology Inc. dsPIC30F5011/5013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 116
... DS70116E-page 114 Preliminary 2004 Microchip Technology Inc. ...
Page 117
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 115 ...
Page 118
... DS70116E-page 116 Preliminary 2004 Microchip Technology Inc. ...
Page 119
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 117 ...
Page 120
... NOTES: DS70116E-page 118 Preliminary 2004 Microchip Technology Inc. ...
Page 121
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled ...
Page 122
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70116E-page 120 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register Preliminary SCKD CSCK FSD COFS 0 CSDI CSDO 2004 Microchip Technology Inc. ...
Page 123
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the ...
Page 124
... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length - this will Preliminary LSB 2004 Microchip Technology Inc. ...
Page 125
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. 2004 Microchip Technology Inc. dsPIC30F5011/5013 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 126
... In this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location would be filled with data. Preliminary 2004 Microchip Technology Inc. ...
Page 127
... DCI module. 2004 Microchip Technology Inc. dsPIC30F5011/5013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 128
... This truncation of the time slots limits the A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register will contain one data time slot value. Preliminary 2004 Microchip Technology Inc. ...
Page 129
... TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must keep track of the current AC-Link frame segment. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2 18.7 I ...
Page 130
... DS70116E-page 128 Preliminary 2004 Microchip Technology Inc. ...
Page 131
... AN13 1110 AN14 1111 AN15 V AN1 2004 Microchip Technology Inc. dsPIC30F5011/5013 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 132
... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. Preliminary 2004 Microchip Technology Inc. ...
Page 133
... 5V). Refer to the Electrical Specifications section for minimum T operating conditions. Example 19-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. 2004 Microchip Technology Inc. dsPIC30F5011/5013 EXAMPLE 19-1: Minimum T ADCS<5:0> Therefore, Set ADCS<5:0> Actual T If SSRC< ...
Page 134
... The 12-bit data can be read in one of four different formats. The FORM<1:0> bits select the format. Each of the output formats translates to a 16-bit result on the data bus. Preliminary ≤ 3 kΩ HOLD C = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. A/ 2004 Microchip Technology Inc. ...
Page 135
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 2004 Microchip Technology Inc. dsPIC30F5011/5013 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 ...
Page 136
... DS70116E-page 134 Preliminary 2004 Microchip Technology Inc. ...
Page 137
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. 2004 Microchip Technology Inc. dsPIC30F5011/5013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 138
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70116E-page 136 Description (1) . (2) . (3) OSC /4 output . (3) . Preliminary 2004 Microchip Technology Inc. (1) . (1) . (1) . ...
Page 139
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI 2004 Microchip Technology Inc. dsPIC30F5011/5013 PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock Switching Secondary Osc ...
Page 140
... Preliminary OSC2 FPR1 FPR0 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 OSC2 1 0 — — (Notes 1, 2) (Notes — — (Notes 1, 2) 2004 Microchip Technology Inc. ...
Page 141
... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7.5 MHz. 2004 Microchip Technology Inc. dsPIC30F5011/5013 TABLE 20-4: TUN<3:0> Bits 0111 ...
Page 142
... Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. Preliminary 2004 Microchip Technology Inc. ...
Page 143
... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 144
... OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70116E-page 142 OST T PWRT T T OST PWRT T OST T T PWRT Preliminary ) DD ): CASE CASE 2 DD 2004 Microchip Technology Inc. ...
Page 145
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. 2004 Microchip Technology Inc. dsPIC30F5011/5013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device configuration bit values (FOS< ...
Page 146
... Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70116E-page 144 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( Preliminary 2004 Microchip Technology Inc. ...
Page 147
... Illegal Operation Reset 0x000000 Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. 2004 Microchip Technology Inc. dsPIC30F5011/5013 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 148
... T timer delay are not applied. In order to have -the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. Preliminary 2004 Microchip Technology Inc. LOCK PWRT , T and T delays POR ...
Page 149
... Upon wake-up from Idle mode, the clock is re-applied to the CPU and instruction execution begins immedi- ately, starting with the instruction following the PWRSAV instruction. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level will be able to wake-up the processor ...
Page 150
... PGD and PGC pin functions in all dsPIC30F devices EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the Debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. Preliminary 2004 Microchip Technology Inc ...
Page 151
... Microchip Technology Inc. dsPIC30F5011/5013 Preliminary DS70116E-page 149 ...
Page 152
... NOTES: DS70116E-page 150 Preliminary 2004 Microchip Technology Inc. ...
Page 153
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ 2004 Microchip Technology Inc. dsPIC30F5011/5013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 154
... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the Programmer’s Reference Manual. Description Preliminary 2004 Microchip Technology Inc. ...
Page 155
... Y data space pre-fetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description Preliminary DS70116E-page 153 ...
Page 156
... Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Preliminary 2004 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z ...
Page 157
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 158
... Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Pre-fetch and store accumulator Preliminary 2004 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None ...
Page 159
... RRC Ws,Wd 67 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 2004 Microchip Technology Inc. dsPIC30F5011/5013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 160
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary 2004 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None 1 1 None ...
Page 161
... L - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 162
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary 2004 Microchip Technology Inc. economical software ...
Page 163
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 164
... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. Preliminary 2004 Microchip Technology Inc. ...
Page 165
... PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. dsPIC30F5011/5013 22.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 166
... NOTES: DS70116E-page 164 Preliminary 2004 Microchip Technology Inc. ...
Page 167
... DD Range Temp Range 4.75-5.5V -40°C to 85°C 4.75-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C 2004 Microchip Technology Inc. dsPIC30F5011/5013 DD (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V DD ) ..........................................................................................................± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 168
... INT I O θ Typ Max Unit Notes 76 °C °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature — V — V V/ms 0-5V in 0.1 sec 0- 2004 Microchip Technology Inc. ...
Page 169
... All I/O pins are configured as Inputs and pulled MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 170
... DD measurements are as follows: OSC1 Preliminary 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS 2004 Microchip Technology Inc. ...
Page 171
... All I/O pins are configured as Inputs and pulled MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) (CONTINUED) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 172
... Preliminary 1 MIPS EC mode 4 MIPS EC mode, 4X PLL 10 MIPS EC mode, 4X PLL 8 MIPS EC mode, 8X PLL 2004 Microchip Technology Inc. ...
Page 173
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I IDLE current is measured with Core off, Clock on and all modules turned off. 2004 Microchip Technology Inc. dsPIC30F5011/5013 ) (CONTINUED) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 174
... Preliminary ) PD (3) Base Power Down Current (3) Watchdog Timer Current: ∆I WDT (3) Timer 1 w/32 kHz Crystal: ∆ BOR (3) BOR On: ∆I 2004 Microchip Technology Inc. ...
Page 175
... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 176
... SM bus enabled bus disabled V SM bus enabled µA DD PIN 5V µA DD PIN 3V µA ≤ V ≤ PIN Pin at hi-impedance µA ≤ V ≤ PIN DD , Pin at hi-impedance µA ≤ V ≤ PIN DD V µA ≤ V ≤ PIN XT, HS and LP Osc mode 2004 Microchip Technology Inc. ...
Page 177
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS DD V LV10 LVDIF (LVDIF set by hardware) 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...
Page 178
... V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V (Device not in Brown-out Reset) Power Up Time-out 2004 Microchip Technology Inc. ...
Page 179
... DD During Programming Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 180
... DC Spec Section 23.0. Load Condition 2 - for OSC2 Pin 464 Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 2004 Microchip Technology Inc. ...
Page 181
... Measurements are taken ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 182
... Units Conditions MHz EC, XT modes with PLL MHz EC, XT modes with PLL µs % Measured over 100 ms period (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — 2004 Microchip Technology Inc. ...
Page 183
... FRC FRC with x4 PLL FRC with x8 PLL FRC with x16 PLL Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. 2004 Microchip Technology Inc. dsPIC30F5011/5013 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended ...
Page 184
... 4.5-5 +25° 3.0-3 +25° 4.5-5.5 V ≤ ≤ +85° 3.0-3.6 V ≤ ≤ +85° 4.5-5.5 V ≤ ≤ +125° 4.5-5.5 V ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions DD -40°C to +85° -40°C to +85° 2004 Microchip Technology Inc. ...
Page 185
... These parameters are asynchronous events not related to any internal clock edges 2: Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2004 Microchip Technology Inc. dsPIC30F5011/5013 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2 ...
Page 186
... TIMER TIMING CHARACTERISTICS DD V SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70116E-page 184 SY10 SY20 SY13 Preliminary 2004 Microchip Technology Inc. SY13 ...
Page 187
... BGAP Band Gap Start-up Time Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 188
... Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz OSC 6 T — 2004 Microchip Technology Inc. ...
Page 189
... TxCK Input Period Synchronous, CKEXTMRL TC20 T Delay from External TxCK Clock Edge to Timer Increment Note: Timer3 and Timer5 are Type C. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min ...
Page 190
... Preliminary ≤ +85°C for Industrial ≤ +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns — ns — 2004 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2004 Microchip Technology Inc. dsPIC30F5011/5013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 192
... CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. DS70116E-page 190 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 Preliminary CS20 CS21 70 LSb HIGH-Z CS31 LSb IN 2004 Microchip Technology Inc. ...
Page 193
... The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 2 S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 194
... Preliminary CS20 CS70 CS75 LSb CS75 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns — ns — ns Bit clock is input ns — ns — µs Note 1 µs Note 1 µs Note 1 LOAD pF LOAD pF LOAD pF LOAD pF — 2004 Microchip Technology Inc. ...
Page 195
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP21 SP20 BIT14 - - - - - -1 MSb ...
Page 196
... Preliminary SP20 SP21 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — — ns — 2004 Microchip Technology Inc. ...
Page 197
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 SP70 SP73 SP72 MSb ...
Page 198
... SCK X (CKP = 0) SP71 X SCK (CKP = 1) MSb X SDO X SDI SDI MSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. DS70116E-page 196 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN Preliminary SP52 SP72 SP73 SP51 2004 Microchip Technology Inc. ...
Page 199
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. 2004 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 200
... C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. DS70116E-page 198 IM11 IM10 IM26 IM25 IM40 Preliminary IM34 IM33 Stop Condition IM21 IM33 IM45 2004 Microchip Technology Inc. ...