DSPIC30F5011T-20I/PT Microchip Technology, DSPIC30F5011T-20I/PT Datasheet
DSPIC30F5011T-20I/PT
Specifications of DSPIC30F5011T-20I/PT
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DSPIC30F5011T-20I/PT Summary of contents
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... EEPROM may be corrupted 2. Decimal Adjust Instruction The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>). © 2005 Microchip Technology Inc. dsPIC30F5011/5013 3. PSV Operations Using SR In certain instructions, fetching one of the operands from program memory using Program Space Visibility (PSV) will corrupt specific bits in the Status Register, SR ...
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... NC, L0 DAW.b w2 BSET.b SR, #C BRA L1 L0:DAW.b w2 L1: .... Low Byte (Even Address) 0x7FFC00 0x7FFC02 0x7FFC04 0x7FFC06 0x7FFC08 0x7FFC0A Instruction DAW.b ;First BCD number ;Second BCD number ;If C set ;If not,do DAW and ;set the carry bit ;and exit © 2005 Microchip Technology Inc. ...
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... ASM30 assembler, the application may perform a PSV access to move the source operand from program memory to RAM register prior to performing the operations listed in Table 1. The work around for Example 3 is demonstrated in Example 4. © 2005 Microchip Technology Inc. dsPIC30F5011/5013 Examples of Incorrect Operation ;See Note 1 ;See Note 1 ;See Note 1 ...
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... SFR (I2CCON in this case). This function should only be used to read the I2CCON Special Function Register. For example, the I2CCON register can be read using a function call: reg_value = __builtin_readsfr(&I2CCON); where ‘reg_value’ is the 16-bit value read from the SFR. © 2005 Microchip Technology Inc. ...
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... I2CTRN register can be written using a function call: __builtin_writesfr(&I2CTRN, reg_value); where ‘reg_value’ is the 16-bit value to be written to the SFR. © 2005 Microchip Technology Inc. dsPIC30F5011/5013 7. Module: UART – Write Operations on U1MODE and U2MODE SFRs Data writes to the U1MODE and U2MODE Special ...
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... Use x8 PLL or x16 PLL mode of operation and ) of DD set final device clock speed using the POST<1:0> oscillator postscaler control bits (OSCCON<7:6>). 2. Use the EC without PLL Clock mode with a suitable clock frequency to obtain the equivalent x4 PLL clock rate. is 2.5-3.0V, the x4 PLL input © 2005 Microchip Technology Inc. ...
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... EXAMPLE 11: #define DISI_PROTECT(X) { __asm__ volatile ("DISI #0x1FFF");\ X; DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); © 2005 Microchip Technology Inc. dsPIC30F5011/5013 Work around The user may disable interrupt nesting or execute a DISI instruction before modifying the CPU IPL or Interrupt 1 setting. A minimum DISI value required if the DISI is executed immediately before the CPU IPL or Interrupt 1 is modified, as shown in Example 9 ...
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... FOSC Configuration register may not be set up for FRC w/PLL 4x/8x/16x modes. Work around None. In future revisions of silicon, port pin RC15 may also be configured for digital I/O when the FPR<4:0> bits in the FOSC Configuration register are set up for FRC w/PLL 4x/8x/16x modes. DS80210E-page 8 © 2005 Microchip Technology Inc. ...
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... Revision D (3/2005) Added silicon issues 8 (Data Converter Interface – Idle), 9 (High I During Row Erase of Program Flash DD Memory), 10 (PLL) and 11 (Interrupt Controller – Sequential Interrupts). Revision E (4/2005) Added silicon issue 12 (Using OSC2/RC15 pin for Digital I/O). © 2005 Microchip Technology Inc. dsPIC30F5011/5013 DS80210E-page 9 ...
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... NOTES: DS80210E-page 10 © 2005 Microchip Technology Inc. ...
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... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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