PIC18F4439-E/P Microchip Technology, PIC18F4439-E/P Datasheet - Page 283
PIC18F4439-E/P
Manufacturer Part Number
PIC18F4439-E/P
Description
IC PIC MCU FLASH 6KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 283 of 322
- Download datasheet (7Mb)
TABLE 23-16: I
2002 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Param.
No.
2: A Fast mode I
T
T
T
T
T
T
T
T
T
T
T
C
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
T
released.
SU
SU
SU
AA
Symbol
HIGH
LOW
R
F
HD
HD
BUF
B
R
:
:
:
max. + T
:
:
STA
DAT
STO
STA
DAT
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time 100 kHz mode
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
2
:
DAT
C bus device can be used in a Standard mode I
= 1000 + 250 = 1250 ns (according to the Standard mode I
Characteristic
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Preliminary
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
2
CY
CY
C bus system, but the requirement T
B
B
1000
1000
3500
Max
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
Units
pF
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
PIC18FXX39
PIC18FXXX must operate at a
minimum of 1.5 MHz
PIC18FXXX must operate at a
minimum of 10 MHz
PIC18FXXX must operate at a
minimum of 1.5 MHz
PIC18FXXX must operate at a
minimum of 10 MHz
C
10 to 400 pF
V
V
Only relevant for Repeated
START condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
B
DD
DD
is specified to be from
≥ 4.2V
≥ 4.2V
Conditions
DS30485A-page 281
SU
:
DAT
≥ 250 ns
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