PIC18F4439-E/P Microchip Technology, PIC18F4439-E/P Datasheet - Page 197
PIC18F4439-E/P
Manufacturer Part Number
PIC18F4439-E/P
Description
IC PIC MCU FLASH 6KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 197 of 322
- Download datasheet (7Mb)
20.0
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving Operating
modes and offer code protection. These are:
• OSC Selection
• RESET
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18FXX39 devices have a Watchdog Timer,
which is permanently enabled via the configuration bits,
or software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
2002 Microchip Technology Inc.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
SPECIAL FEATURES OF THE
CPU
Preliminary
20.1
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using Table Reads and
Table Writes.
Programming the configuration registers is done in a
manner similar to programming the FLASH memory
(see Section 5.5.1). The only difference is the configu-
ration registers are written a byte at a time. The
sequence of events for programming configuration
registers is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Re-enable interrupts.
Load table pointer with address of configuration
register being written.
Write a single byte using the TBLWT instruction.
Set EEPGD to point to program memory, set the
CFGS bit to access configuration registers, and
set WREN to enable byte writes.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
CPU will stall for duration of write (approximately
2 ms using internal timer).
Execute a NOP.
Configuration Bits
PIC18FXX39
DS30485A-page 195
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