PIC18LF8621T-I/PT Microchip Technology, PIC18LF8621T-I/PT Datasheet - Page 78
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF8621T-I/PT
Manufacturer Part Number
PIC18LF8621T-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F6525-IPT.pdf
(396 pages)
Specifications of PIC18LF8621T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8621T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (8Mb)
PIC18F6525/6621/8525/8621
6.2.4
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
FIGURE 6-5:
DS39612B-page 76
AD<15:0>
A<19:16>
Instruction
Execution
AD<15:0>
A<19:16>
Memory
Cycle
Instruction
Execution
ALE
Memory
CE
OE
WRH
Apparent Q
WRL
Cycle
16-BIT MODE TIMING
BA0
ALE
OE
CE
Actual Q
‘1’
‘0’
‘1’
Q1
EXTERNAL MEMORY BUS TIMING FOR TBLRD
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
(EXTENDED MICROCONTROLLER MODE)
Opcode Fetch
INST(PC – 2)
from 000100h
Q1
Q1
Q2
TBLRD*
3AABh
TBLRD Cycle 1
Opcode Fetch
from 007556h
Q2
Q2
Q3
MOVLW 55h
00h
Q4
Q3
Q3
0E55h
Q1
Q4
Q4
TBLRD Cycle 1
Opcode Fetch
from 000102h
MOVLW 55h
Q2
Q1
Q1
Q3
CF33h
Q2
Q2
Q4
Q3
Q3
Q1
TBLRD Cycle 2
from 199E67h
CF33h
Table Read
from 199E67h
TBLRD Cycle 2
TBLRD 92h
of 92h
Q2
Q4
Q4
0Ch
0Ch
Q3
Q4
Q1
9256h
9256h
Q4
Q4
Q2
1 T
2005 Microchip Technology Inc.
Q1
CY
Wait
Opcode Fetch
from 000104h
Q4
Q3
ADDLW 55h
Q2
MOVLW
Q4
Q4
Q3
‘1’
‘1’
‘0’
Q4
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