PIC18LF8621T-I/PT Microchip Technology, PIC18LF8621T-I/PT Datasheet - Page 234
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF8621T-I/PT
Manufacturer Part Number
PIC18LF8621T-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F6525-IPT.pdf
(396 pages)
Specifications of PIC18LF8621T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8621T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6525/6621/8525/8621
19.4.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register; if the RC1IE enable bit is set, the
interrupt generated will wake the chip from Low-Power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS39612B-page 232
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
Note 1:
Name
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
EUSART SYNCHRONOUS SLAVE
RECEPTION
Enhanced USARTx Baud Rate Generator Register High Byte
Enhanced USARTx Baud Rate Generator Register Low Byte
Enhanced USARTx Receive Register
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
—
—
—
—
(1)
(1)
(1)
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
—
—
TMR0IE
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
—
INT0IE
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SCKP
Bit 4
TMR4IF
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111
CCP5IF
BRGH
FERR
Bit 2
—
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCxIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCxIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCxIE was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IF TMR1IF
CCP4IF
INT0IF
OERR
TRMT
WUE
Bit 1
CCP3IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
2005 Microchip Technology Inc.
0000 000x
0000 0000
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
POR, BOR
Value on
0000 000u
0000 0000
0000 0000
1111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
Value on
all other
Resets
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