PIC18LF4439T-I/ML Microchip Technology, PIC18LF4439T-I/ML Datasheet - Page 181

• Manufacturer Part Number: PIC18LF4439T-I/ML
• Description: IC PIC MCU 6KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4439T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 640 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 640 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
17.4.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
 2002 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
USART Synchronous Slave Mode
Shaded cells are not used for Synchronous Slave Transmission.
clear.
USART SYNCHRONOUS SLAVE
TRANSMIT
USART Transmit Register
PSPIE
PSPIP
Baud Rate Generator Register
PSPIF
SPEN
CSRC
GIEH
Bit 7
GIE/
(1)
(1)
(1)
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
CREN ADDEN
SYNC
Bit 4
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
Preliminary
RBIE
Bit 3
—
TMR0IF
BRGH
FERR
Bit 2
—
—
—
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IF TMR1IF 0000 0000 0000 0000
TMR2IE TMR1IE 0000 0000 0000 0000
TMR2IP TMR1IP 0000 0000 0000 0000
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
PIC18FXX39
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
DS30485A-page 179
All Other
Value on
RESETS