PIC16F874A-E/ML Microchip Technology, PIC16F874A-E/ML Datasheet - Page 81
PIC16F874A-E/ML
Manufacturer Part Number
PIC16F874A-E/ML
Description
IC MCU FLASH 4KX14 A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F874A-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 81 of 234
- Download datasheet (5Mb)
9.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
9.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 9-2:
2003 Microchip Technology Inc.
INTCON
PIR1
PIE1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Note 1:
Name
Shaded cells are not used by the MSSP in SPI mode.
The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
PSPIE
Synchronous Serial Port Receive Buffer/Transmit Register
PSPIF
WCOL
GIEH
Bit 7
SMP
GIE/
—
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
PORTA Data Direction Register
SSPOV SSPEN
PEIE/
ADIE
GIEL
ADIF
Bit 6
CKE
TMR0IE INT0IE
RCIE
RCIF
Bit 5
D/A
Bit 4
TXIF
TXIE
CKP
P
SSPM3
SSPIE
SSPIF
RBIE
Bit 3
S
TMR0IF
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPM2
9.3.10
Table 9-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 9-1:
There is also a SMP bit which controls when the data is
sampled.
Bit 2
R/W
Standard SPI Mode
Terminology
0, 0
0, 1
1, 0
1, 1
SSPM1 SSPM0 0000 0000 0000 0000
INT0IF
Bit 1
BUS MODE COMPATIBILITY
UA
SPI BUS MODES
RBIF
Bit 0
PIC16F87XA
BF
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
0000 0000 0000 0000
CKP
POR, BOR
Control Bits State
Value on
0
0
1
1
DS39582B-page 79
Value on
all other
Resets
CKE
1
0
1
0
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