PIC16F874A-E/ML Microchip Technology, PIC16F874A-E/ML Datasheet - Page 228
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PIC16F874A-E/ML
Manufacturer Part Number
PIC16F874A-E/ML
Description
IC MCU FLASH 4KX14 A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F874A-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F87XA
Special Function Registers ................................................ 19
Special Function Registers (SFRs) .................................... 19
Speed, Operating ................................................................. 1
SPI Mode ..................................................................... 71, 77
SPI Mode Requirements .................................................. 190
SS ...................................................................................... 71
SSP
SSPADD Register .............................................................. 20
SSPBUF Register .............................................................. 19
SSPCON Register .............................................................. 19
SSPCON2 Register ............................................................ 20
SSPIF ................................................................................. 26
SSPOV ............................................................................. 101
SSPSTAT Register ............................................................ 20
Stack .................................................................................. 30
Status Register
Synchronous Master Reception
Synchronous Master Transmission
Synchronous Serial Port Interrupt ...................................... 26
Synchronous Slave Reception
Synchronous Slave Transmission
T
T1CKPS0 Bit ...................................................................... 57
T1CKPS1 Bit ...................................................................... 57
T1CON Register ................................................................. 19
T1OSCEN Bit ..................................................................... 57
T1SYNC Bit ........................................................................ 57
T2CKPS0 Bit ...................................................................... 61
T2CKPS1 Bit ...................................................................... 61
T2CON Register ................................................................. 19
T
Time-out Sequence .......................................................... 148
DS39582B-page 226
AD
................................................................................... 131
Associated Registers ................................................. 79
Bus Mode Compatibility ............................................. 79
Effects of a Reset ....................................................... 79
Enabling SPI I/O ......................................................... 75
Master Mode .............................................................. 76
Master/Slave Connection ........................................... 75
Serial Clock ................................................................ 71
Serial Data In ............................................................. 71
Serial Data Out ........................................................... 71
Slave Select ............................................................... 71
Slave Select Synchronization ..................................... 77
Sleep Operation ......................................................... 79
SPI Clock ................................................................... 76
Typical Connection ..................................................... 75
SPI Master/Slave Connection .................................... 75
R/W Bit ................................................................. 84, 85
Overflows ................................................................... 30
Underflow ................................................................... 30
C Bit ........................................................................... 22
DC Bit ......................................................................... 22
IRP Bit ........................................................................ 22
PD Bit ................................................................. 22, 147
RP1:RP0 Bits ............................................................. 22
TO Bit ................................................................. 22, 147
Z Bit ............................................................................ 22
Associated Registers ............................................... 123
Associated Registers ............................................... 122
Associated Registers ............................................... 125
Associated Registers ............................................... 125
Timer0 ................................................................................ 53
Timer0 and Timer1 External Clock Requirements ........... 185
Timer1 ................................................................................ 57
Timer2 ................................................................................ 61
Timing Diagrams
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit) ....................... 23
Clock Source Select (T0CS Bit) ................................. 23
External Clock ............................................................ 54
Interrupt ..................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 24
Overflow Flag (TMR0IF Bit) ................................24, 154
Overflow Interrupt .................................................... 154
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
Associated Registers ................................................. 60
Asynchronous Counter Mode .................................... 59
Counter Operation ..................................................... 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 59
Prescaler .................................................................... 60
Resetting of Timer1 Registers ................................... 60
Resetting Timer1 Using a CCP Trigger Output ......... 59
Synchronized Counter Mode ..................................... 58
TMR1H ...................................................................... 59
TMR1L ....................................................................... 59
Associated Registers ................................................. 62
Output ........................................................................ 62
Postscaler .................................................................. 61
Prescaler .................................................................... 61
Prescaler and Postscaler ........................................... 62
A/D Conversion ........................................................ 195
Acknowledge Sequence .......................................... 104
Asynchronous Master Transmission ........................ 116
Asynchronous Master Transmission
Asynchronous Reception ......................................... 118
Asynchronous Reception with
Asynchronous Reception with
Baud Rate Generator with Clock Arbitration .............. 98
BRG Reset Due to SDA Arbitration During
Brown-out Reset ...................................................... 184
Bus Collision During a Repeated
Bus Collision During Repeated
Bus Collision During Start Condition
Bus Collision During Start Condition
Bus Collision During Stop Condition
Bus Collision During Stop Condition
Bus Collision for Transmit and Acknowledge .......... 105
Capture/Compare/PWM (CCP1 and CCP2) ............ 186
CLKO and I/O .......................................................... 183
Clock Synchronization ............................................... 91
External Clock .......................................................... 182
First Start Bit .............................................................. 99
Reading and Writing to ...................................... 59
Capacitor Selection ............................................ 59
(Back to Back) ................................................. 116
Address Byte First ........................................... 120
Address Detect ................................................ 120
Start Condition ................................................. 107
Start Condition (Case 1) .................................. 108
Start Condition (Case 2) .................................. 108
(SCL = 0) ......................................................... 107
(SDA Only) ....................................................... 106
(Case 1) ........................................................... 109
(Case 2) ........................................................... 109
2003 Microchip Technology Inc.