ATMEGA162L-8PI Atmel, ATMEGA162L-8PI Datasheet - Page 70

• Manufacturer Part Number: ATMEGA162L-8PI
• Description: IC MCU AVR 16K 3V 8MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Alternate Functions Of Port B
70
ATmega162(V/U/L)
The Port B pins with alternate functions are shown in Table 32.
Table 32. Port B Pins Alternate Functions
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con-
trolled by the PORTB7 bit.
• MISO – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-
trolled by the PORTB6 bit.
• MOSI – Port B, Bit 5
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be con-
trolled by the PORTB5 bit.
• SS/OC3B – Port B, Bit 4
SS: Slave Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is
driven low. When the SPI is enabled as a Master, the data direction of this pin is con-
trolled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be
controlled by the PORTB4 bit.
Port Pin
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Alternate Functions
SCK (SPI Bus Serial Clock)
MISO (SPI Bus Master Input/Slave Output)
MOSI (SPI Bus Master Output/Slave Input)
SS (SPI Slave Select Input)
OC3B (Timer/Counter3 Output Compare Match Output)
AIN1 (Analog Comparator Negative Input)
TXD1 (USART1 Output Pin)
AIN0 (Analog Comparator Positive Input)
RXD1 (USART1 Input Pin)
T1 (Timer/Counter1 External Counter Input)
OC2 (Timer/Counter2 Output Compare Match Output)
T0 (Timer/Counter0 External Counter Input)
OC0 (Timer/Counter0 Output Compare Match Output)
clk
I/O
(Divided System Clock)
2513C–AVR–09/02