ATMEGA162L-8AI Atmel, ATMEGA162L-8AI Datasheet - Page 133
ATMEGA162L-8AI
Manufacturer Part Number
ATMEGA162L-8AI
Description
IC MCU AVR 16K 3V 8MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162L-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Extended Timer/Counter
Interrupt Mask Register –
ETIMSK
2513C–AVR–09/02
(1)
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
ICF1 flag, located in TIFR, is set.
Note:
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
ICF3 flag, located in TIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
OCF3A flag, located in TIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the
OCF3B flag, located in TIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 55.) is executed when the TOV3 flag, located
in TIFR, is set.
Bit
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only
Timer3 bits are described in this section. The remaining bits are described in their
respective Timer sections.
R
7
0
6
R
0
TICIE3
R/W
5
0
OCIE3A
R/W
4
0
OCIE3B
R/W
3
0
ATmega162(V/U/L)
TOIE3
R/W
2
0
R
1
–
0
R
0
–
0
ETIMSK
133
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