ATMEGA8535L-8MI Atmel, ATMEGA8535L-8MI Datasheet - Page 18

• Manufacturer Part Number: ATMEGA8535L-8MI
• Description: IC AVR MCU 8K LV 8MHZ IND 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Data Memory Access Times
EEPROM Data Memory
EEPROM Read/Write Access
18
ATmega8535(L)
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
10.
Figure 10. On-chip Data SRAM Access Cycles
The ATmega8535 contains 512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has
an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 237 contains a detailed description on EEPROM Pro-
gramming in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, V
causes the device, for some period of time, to run at a voltage lower than specified as
minimum for the clock frequency used, see “Preventing EEPROM Corruption” on page
22 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
Address
clk
Data
Data
WR
CPU
RD
Compute Address
T1
Memory Access Instruction
CC
is likely to rise or fall slowly on Power-up/down. This
Address valid
T2
CPU
cycles as described in Figure
Next Instruction
T3
2502K–AVR–10/06