ATMEGA8535-16JC Atmel, ATMEGA8535-16JC Datasheet - Page 195
![IC AVR MCU 8K 16MHZ COM 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535-16JC
Manufacturer Part Number
ATMEGA8535-16JC
Description
IC AVR MCU 8K 16MHZ COM 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16JC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
2 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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2502K–AVR–10/06
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond
when addressed by a Master. If the LSB is set, the TWI will respond to the general call
address (0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgement of the device’s own slave address or the general call
address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode
is entered. After its own slave address and the write bit have been received, the TWINT
Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in Table 77. The Slave Receiver mode may also be entered if
arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)
to SDA after the next received data byte. This can be used to indicate that the Slave is
not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge
its own slave address. However, the Two-wire Serial Bus is still monitored and address
recognition may resume at any time by setting TWEA. This implies that the TWEA bit
may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the
TWEA bit is set, the interface can still acknowledge its own slave address or the general
call address by using the Two-wire Serial Bus clock as a clock source. The part will then
wake up from sleep and the TWI will hold the SCL clock low during the wake up and
until the TWINT Flag is cleared (by writing it to one). Further data reception will be car-
ried out as normal, with the AVR clocks running as normal. Observe that if the AVR is
set up with a long start-up time, the SCL line may be held low for a long time, blocking
other data transmissions.
Note that the Two-wire Serial Interface Data Register – TWDR – does not reflect the last
byte present on the bus when waking up from these sleep modes.
TWAR
Value
TWCR
Value
TWINT
TWA6
0
TWEA
TWA5
1
TWSTA
TWA4
Device’s Own Slave Address
0
TWSTO
TWA3
0
TWWC
TWA2
0
ATmega8535(L)
TWEN
TWA1
1
TWA0
–
0
TWGCE
TWIE
X
195
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