ATMEGA8535-16JC Atmel, ATMEGA8535-16JC Datasheet - Page 115
![IC AVR MCU 8K 16MHZ COM 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535-16JC
Manufacturer Part Number
ATMEGA8535-16JC
Description
IC AVR MCU 8K 16MHZ COM 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16JC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
2 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Timer/Counter Interrupt Mask
Register – TIMSK
2502K–AVR–10/06
(1)
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the ICF1
Flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 output compare A match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the
OCF1A Flag, located in TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 output compare B match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the
OCF1B Flag, located in TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 46) is executed when the TOV1 Flag, located
in TIFR, is set.
Bit
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only
Timer1 bits are described in this section. The remaining bits are described in their
respective timer sections.
OCIE2
R/W
7
0
TOIE2
R/W
6
0
TICIE1
R/W
5
0
OCIE1A
R/W
4
0
OCIE1B
R/W
3
0
TOIE1
R/W
ATmega8535(L)
2
0
OCIE0
R/W
1
0
TOIE0
R/W
0
0
TIMSK
115
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