ATMEGA32-16AI Atmel, ATMEGA32-16AI Datasheet - Page 274

• Manufacturer Part Number: ATMEGA32-16AI
• Description: IC AVR MCU 32K 16MHZ IND 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPI Serial
Programming
Characteristics
Programming via
the JTAG Interface
Programming Specific
JTAG Instructions
2503Q–AVR–02/11
For Characteristics of SPI module, see
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.
Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in running mode while still allowing In-System
Programming via the JTAG interface. Note that this technique can not be used when using the
JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedi-
cated for this purpose.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
Figure
138.
“SPI Timing Characteristics” on page
ATmega32(L)
291.
274