ATMEGA32-16AI Atmel, ATMEGA32-16AI Datasheet - Page 164

• Manufacturer Part Number: ATMEGA32-16AI
• Description: IC AVR MCU 32K 16MHZ IND 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

USART Baud Rate
Registers – UBRRL
and UBRRH
2503Q–AVR–02/11
• Bit 0 – UCPOL: Clock Polarity
This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 67. UCPOL Bit Settings
The UBRRH Register shares the same I/O location as the UCSRC Register. See the
UBRRH/ UCSRC Registers” on page 158
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when
reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the 8 least significant bits of the USART baud
rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
Bit
Read/Write
Initial Value
UCPOL
0
1
Transmitted Data Changed (Output of
TxD Pin)
Rising XCK Edge
Falling XCK Edge
URSEL
R/W
R/W
15
7
0
0
R/W
14
R
–
6
0
0
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRR[7:0]
section which describes how to access this register.
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxD Pin)
Rising XCK Edge
Falling XCK Edge
R/W
R/W
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
ATmega32(L)
R/W
R/W
8
0
0
0
UBRRH
UBRRL
“Accessing
164