ATMEGA16L-8AI Atmel, ATMEGA16L-8AI Datasheet - Page 238
![IC AVR MCU 16K LV 8MHZ IND44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16L-8AI
Manufacturer Part Number
ATMEGA16L-8AI
Description
IC AVR MCU 16K LV 8MHZ IND44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16L-8AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Table 92. Boundary-scan Signals for the ADC
2466T–AVR–07/10
Signal
Name
COMP
ACLK
ACTEN
ADCBGEN
ADCEN
AMPEN
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
G10
G20
GNDEN
HOLD
IREFEN
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
Direction as Seen
from the ADC
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Comparator Output
Clock signal to gain stages
implemented as Switch-cap filters
Enable path from gain stages to
the comparator
Enable Band-gap reference as
negative input to comparator
Power-on signal to the ADC
Power-on signal to the gain stages
Bit 9 of digital value to DAC
Bit 8 of digital value to DAC
Bit 7 of digital value to DAC
Bit 6 of digital value to DAC
Bit 5 of digital value to DAC
Bit 4 of digital value to DAC
Bit 3 of digital value to DAC
Bit 2 of digital value to DAC
Bit 1 of digital value to DAC
Bit 0 of digital value to DAC
Connect ADC channels 0 - 3 to by-
pass path around gain stages
Enable 10x gain
Enable 20x gain
Ground the negative input to
comparator when true
Sample&Hold signal. Sample
analog signal when low. Hold
signal when high. If gain stages
are used, this signal must go
active when ACLK is high.
Enables Band-gap reference as
AREF signal to DAC
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Recommended
Input when Not
in Use
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
Output Values when Recommended
Inputs are used, and CPU is not
Using the ADC
ATmega16(L)
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
238
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