ATMEGA16L-8AI Atmel, ATMEGA16L-8AI Datasheet - Page 111
![IC AVR MCU 16K LV 8MHZ IND44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16L-8AI
Manufacturer Part Number
ATMEGA16L-8AI
Description
IC AVR MCU 16K LV 8MHZ IND44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16L-8AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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2466T–AVR–07/10
Table 45. Compare Output Mode, Fast PWM
Note:
Table 46
rect or the phase and frequency correct, PWM mode.
Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
Note:
• Bit 3 – FOC1A: Force Output Compare for Channel A
• Bit 2 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase cor-
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM.
PWM Mode” on page 102.
“Phase Correct PWM Mode” on page 104.
COM1A0/COM1B0
COM1A0/COM1B0
0
1
0
1
0
1
0
1
for more details.
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port
operation).
For all other WGM13:0 settings, normal port
operation, OCnA/OCnB disconnected.
Clear OC1A/OC1B on compare match, set
OC1A/OC1B at BOTTOM,
(non-inverting mode)
Set OC1A/OC1B on compare match, clear
OC1A/OC1B at BOTTOM,
(inverting mode)
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 9 or 14: Toggle OCnA on
Compare Match, OCnB disconnected (normal
port operation).
For all other WGM13:0 settings, normal port
operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match when
up-counting. Set OC1A/OC1B on compare
match when downcounting.
Set OC1A/OC1B on compare match when up-
counting. Clear OC1A/OC1B on compare
match when downcounting.
(1)
for more details.
ATmega16(L)
See “Fast
(1)
111
See
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