PIC17C766-33E/L Microchip Technology, PIC17C766-33E/L Datasheet - Page 209
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C766-33E/L
Manufacturer Part Number
PIC17C766-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM84PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164318 - MODULE SKT MPLAB PM3 84PLCCDVA17XL841 - DEVICE ADAPTER FOR PIC17C762DM173001 - KIT DEVELOPMENT PICDEM17AC164027 - ADAPTER PICSTART PLUS 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
PC Address
WREG
REG
If REG
If REG
Q1
Q1
No
PC
PC
register ’f’
operation
Compare f with WREG,
skip if f = WREG
[ label ] CPFSEQ
0
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of WREG by
performing an unsigned subtraction.
If ’f’ = WREG, then the fetched instruc-
tion is discarded and a NOP is executed
instead, making this a two-cycle
instruction.
1
1 (2)
HERE
NEQUAL
EQUAL
Read
0011
Q2
Q2
No
=
=
=
=
=
=
f
255
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
CPFSEQ REG
:
:
0001
operation
Process
Data
Q3
Q3
No
ffff
f
operation
operation
Q4
Q4
No
No
ffff
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
operation
Decode
PC
WREG
If REG
If REG
Q1
Q1
No
PC
PC
register ’f’
operation
Compare f with WREG,
skip if f > WREG
[ label ] CPFSGT
0
(f)
skip if (f) > (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of the WREG
by performing an unsigned subtraction.
If the contents of ’f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
1 (2)
HERE
NGREATER
GREATER
Read
0011
Q2
Q2
No
=
=
>
=
£
f
=
PIC17C7XX
WREG),
255
Address (HERE)
?
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
0010
CPFSGT REG
:
:
operation
Process
Data
Q3
Q3
No
DS30289B-page 209
ffff
f
operation
operation
Q4
Q4
No
No
ffff
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