PIC17C766-33E/L Microchip Technology, PIC17C766-33E/L Datasheet - Page 201
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PIC17C766-33E/L
Manufacturer Part Number
PIC17C766-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM84PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164318 - MODULE SKT MPLAB PM3 84PLCCDVA17XL841 - DEVICE ADAPTER FOR PIC17C762DM173001 - KIT DEVELOPMENT PICDEM17AC164027 - ADAPTER PICSTART PLUS 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 201 of 304
- Download datasheet (6Mb)
TABLE 18-2:
Mnemonic,
Operands
TSTFSZ
XORWF
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2000 Microchip Technology Inc.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOP is executed.
(WREG) is required to be affected, then f = WREG must be specified.
PC (PCL).
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
f
f,d
f,b
f,b
f,b
f,b
f,b
k
k
k
—
k
k
k
k
k
k
k
—
k
—
—
k
k
PIC17CXXX INSTRUCTION SET (CONTINUED)
Description
Test f, skip if 0
Exclusive OR WREG with f
Bit Clear f
Bit Set f
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
ADD literal to WREG
AND literal with WREG
Subroutine Call
Clear Watchdog Timer
Unconditional Branch
Inclusive OR literal with WREG
Long Call
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP mode
Subtract WREG from literal
Exclusive OR literal with WREG
Cycles
1 (2)
1 (2)
1 (2)
1
1
1
1
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
0011
0000
1000
1000
1001
1001
0011
1011
1011
111k
0000
110k
1011
1011
1011
1011
1011
1011
0000
1011
0000
0000
1011
1011
MSb
16-bit Opcode
0011 ffff ffff
110d ffff ffff
1bbb ffff ffff
0bbb ffff ffff
1bbb ffff ffff
0bbb ffff ffff
1bbb ffff ffff
0001 kkkk kkkk
0101 kkkk kkkk
kkkk kkkk kkkk
0000 0000 0100
kkkk kkkk kkkk
0011 kkkk kkkk
0111 kkkk kkkk
1000 uuuu kkkk
101x kkkk uuuu
0000 kkkk kkkk
1100 kkkk kkkk
0000 0000 0101
0110 kkkk kkkk
0000 0000 0010
0000 0000 0011
0010 kkkk kkkk
0100 kkkk kkkk
PIC17C7XX
LSb
Status
Affected
OV,C,DC,Z
OV,C,DC,Z
DS30289B-page 201
GLINTD
TO, PD
TO, PD
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
Z
Notes
6,8
6,8
6,8
4,7
7
7
7
7
7
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