PIC17C766-16E/PT Microchip Technology, PIC17C766-16E/PT Datasheet - Page 215
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C766-16E/PT
Manufacturer Part Number
PIC17C766-16E/PT
Description
IC MCU CMOS 16MHZ 16K EPRM80TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-16E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-16E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
(WREG) .OR. (f)
Z
Inclusive OR WREG with register ’f’. If
’d’ is 0, the result is placed in WREG. If
’d’ is 1, the result is placed back in
register ’f’.
1
1
IORWF
Read
0000
Q2
0x13
0x91
0x13
0x93
f
[0,1]
255
RESULT, 0
IORWF
100d
Process
Data
Q3
ffff
f,d
(dest)
destination
Write to
Q4
ffff
LCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
operation
Decode
SUBROUTINE =
PC
PC
Q1
No
operation
Long Call
[ label ]
0
PC + 1
k
None
LCALL allows an unconditional subrou-
tine call to anywhere within the 64K
program memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address are embedded
in the instruction. The upper 8-bits of
PC are loaded from PC high holding
latch, PCLATH.
1
2
MOVLW
MOVPF
LCALL
literal ’k’
Read
1011
Q2
No
=
=
k
PCL, (PCLATH)
PIC17C7XX
255
16-bit Address
?
Address (SUBROUTINE)
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
LCALL
TOS;
0111
operation
Process
Data
Q3
No
DS30289B-page 215
k
kkkk
register PCL
PCH
operation
Write
Q4
No
kkkk
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