PIC17C766-16E/PT Microchip Technology, PIC17C766-16E/PT Datasheet - Page 170
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PIC17C766-16E/PT
Manufacturer Part Number
PIC17C766-16E/PT
Description
IC MCU CMOS 16MHZ 16K EPRM80TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-16E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-16E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
15.2.18
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA, by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted and
the SSPBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I
tion by asserting a START condition.
FIGURE 15-34:
DS30289B-page 170
SDA
SCL
BCLIF
2
2
C port to its IDLE state (Figure 15-34).
C bus is free, the user can resume communica-
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0.
SDA released
by master.
SDA line pulled low
by another source.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine,
and if the I
nication by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the
I
STAT register, or the bus is idle and the S and P bits
are cleared.
2
C bus can be taken when the P bit is set in the SSP-
2
C bus is free, the user can resume commu-
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2000 Microchip Technology Inc.
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