ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 202

• Manufacturer Part Number: ATMEGA323-8PI
• Description: IC AVR MCU 32K 8MHZ IND 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PI

Programming via the
JTAG Interface
Programming specific
JTAG instructions
AVR_RESET ($C)
PROG_ENABLE ($4)
PROG_COMMANDS ($5)
PROG_PAGELOAD ($6)
202
ATmega323(L)
Programming through the JTAG Interface requires control of the four JTAG specific
pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG Interface, the JTAGEN Fuse must be programmed. The
device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR
must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.
Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available
for programming. This provides a means of using the JTAG pins as normal port pins in
running mode while still allowing In-System Programming via the JTAG interface. Note
that this technique can not be used when using the JTAG pins for Boundary-Scan or
On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is four bit wide, supporting up to 16 instructions. The JTAG
instructions useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO for
each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can
also be used as an idle state between JTAG sequences.
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode
or taking the device out from the Reset mode. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic 'one' in the Reset Chain. The output from this
chain is not latched.
The active states are:
•
The AVR specific public JTAG instruction for enabling programming via the JTAG port.
The 16 bit Programming Enable Register is selected as Data Register. The active states
are the following:
•
•
The AVR specific public JTAG instruction for entering programming commands via the
JTAG port. The 15-bit Programming Command Register is selected as Data Register.
The active states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the
JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as Data Register.
This is a virtual scan chain with length equal to the number of bits in one Flash page.
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state
Shift-DR: The Reset Register is shifted by the TCK input.
Shift-DR: The programming enable signature is shifted into the Data Register.
Update-DR: The programming enable signature is compared to the correct value,
and programming mode is entered if the signature is valid.
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs
Run-Test/Idle: One clock cycle is generated, executing the applied command (not
always required, see Table 71 below).
1457G–AVR–09/03