ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 157
ATMEGA323-8PI
Manufacturer Part Number
ATMEGA323-8PI
Description
IC AVR MCU 32K 8MHZ IND 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8PI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238PI
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JTAG Interface and
the On-chip Debug
System
Features
Overview
1457G–AVR–09/03
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The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
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A brief description is given in the following sections. Detailed descriptions for Program-
ming via the JTAG interface, and using the Boundary-Scan Chain can be found in the
sections “Programming via the JTAG Interface” on page 202 and “IEEE 1149.1 (JTAG)
Boundary-Scan” on page 164, respectively. The On-chip Debug support is considered
being private JTAG instructions, and distributed within ATMEL and to selected third
party vendors only.
Figure 85 shows a block diagram of the JTAG interface and the On-chip Debug system.
The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers
as the scan chain (Shift Register) between the TDI – input and TDO – output. The
Instruction Register holds JTAG instructions controlling the behavior of a Data Register.
Of the Data Registers, the ID-Register, Bypass Register, and the Boundary-Scan Chain
are used for board-level testing. The JTAG Programming Interface (actually consisting
of several physical and virtual Data Registers) is used for Serial Programming via the
JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-
chip debugging only.
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-Scan Capabilities According to the JTAG Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
Testing PCBs by using the JTAG Boundary-Scan Capability.
Programming the Non-volatile Memories, Fuses and Lock bits.
On-chip Debugging.
®
ATmega323(L)
157
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