ATMEGA161-8AI Atmel, ATMEGA161-8AI Datasheet - Page 21

• Manufacturer Part Number: ATMEGA161-8AI
• Description: IC AVR MCU 16K 8MHZ IND 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618AI

Status Register – SREG
1228D–AVR–02/07
All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general pur-
pose working registers and the I/O space. I/O Registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
SRAM, $20 must be added to this address. All I/O Register addresses throughout this
document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the Flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The I/O and Peripherals Control Registers are explained in the following sections.
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
• Bit 7
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable bit is cleared (zero), none of the interrupts are enabled indepen-
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set description for detailed information.
• Bit 3
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set Description for detailed information.
Bit
$3F ($5F)
Read/Write
Initial Value
–
–
–
–
–
I: Global Interrupt Enable
T: Bit Copy Storage
H: Half Carry Flag
S: Sign Bit, S = N ⊕ V
V: Two’s Complement Overflow Flag
R/W
7
0
I
R/W
6
T
0
R/W
H
5
0
R/W
4
S
0
R/W
V
3
0
R/W
N
2
0
ATmega161(L)
R/W
1
Z
0
R/W
C
0
0
SREG
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