ATTINY11L-2PI Atmel, ATTINY11L-2PI Datasheet - Page 7

• Manufacturer Part Number: ATTINY11L-2PI
• Description: IC AVR MCU 1K 2MHZ LV IND 8-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY11L-2PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Data Converters: -
• Connectivity: -
• Other names: ATTINY11L2PI

ALU – Arithmetic Logic
Unit
Subroutine and Interrupt
Hardware Stack
1006F–AVR–06/07
Figure 3. The ATtiny11/12 AVR RISC Architecture
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
r a t e i n t e r r u p t v e c t o r i n t h e i n t e r r u p t v e c t o r t a b le a t t h e b e g i n n i n g o f t h e
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
The high-performance AVR ALU operates in direct connection with all the 32 general-
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the register file are executed. The ALU operations are divided into three main
categories – arithmetic, logic and bit-functions. Some microcontrollers in the AVR prod-
uct family feature a hardware multiplier in the arithmetic part of the ALU.
The ATtiny11/12 uses a 3-level-deep hardware stack for subroutines and interrupts. The
hardware stack is 9 bits wide and stores the program counter (PC) return address while
subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and
the data in the other stack levels 1-2 are pushed one level deeper in the stack. When a
RET or RETI instruction is executed the returning PC is fetched from stack level 0, and
the data in the other stack levels 1-2 are popped one level in the stack.
If more than three subsequent subroutine calls or interrupts are executed, the first val-
ues written to the stack are overwritten. Pushing four return addresses A1, A2, A3, and
A4, followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more
A2 from the hardware stack.
Control Lines
Instruction
Instruction
512 x 16
Program
Register
Decoder
Flash
Direct Addressing
8-bit Data Bus
Program
Counter
64 x 8 EEPROM
(ATtiny12 only)
Registers
and Test
General-
purpose
Status
32 x 8
ALU
ATtiny11/12
(ATtiny12 only)
Timer/Counter
Comparator
Registers
Watchdog
Interrupt
I/O Lines
SPI Unit
Control
Analog
Timer
8-bit
Unit
6
7