AT89LS53-12JI Atmel, AT89LS53-12JI Datasheet
AT89LS53-12JI
Specifications of AT89LS53-12JI
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AT89LS53-12JI Summary of contents
Page 1
... The on-chip downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface conventional nonvol- atile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89LS53 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control appli- cations. ...
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... Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. AT89LS53 2 33 P0.4 (AD4) 32 P0.5 (AD5 ...
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... INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR PORT 1 SPI PROGRAM LATCH PORT LOGIC PORT 1 DRIVERS P1.0 - P1.7 AT89LS53 3 ...
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... Port 3 pins that are externally being pulled low will source current (I ) because of the pullups. IL Port 3 also serves the functions of various special features of the AT89LS53, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification. AT89LS53 4 ...
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... XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. AT89LS53 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H ...
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... CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX CP/RL2 when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89LS53 6 SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5) ...
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... Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET. PS0 reserved reserved AT89LS53 Reset Value = 0000 0010B DPS WDTRST WDTEN ...
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... SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. AT89LS53 8 DORD ...
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... Bit 7 6 Data Memory - RAM The AT89LS53 implements 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...
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... Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS53 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.” Timer 2 Timer bit Timer/Counter that can operate as either a timer or an event counter ...
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... The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. — — — AT89LS53 Reset Value = XXXX XX00B — T2OE DCEN ...
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... Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 4. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC T2 PIN TRANSITION DETECTOR T2EX PIN AT89LS53 12 C/ TH2 CONTROL TR2 C/ RCAP2H RCAP2L EXF2 CONTROL EXEN2 TIMER 1 OVERFLOW ÷ 2 "0" "1" ...
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... The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Oscillator Frequency = --------------------------------------------------------------------------------------------- - × Baud Rate 32 65536 RCAP2H,RCAP2L – AT89LS53 ) ] 13 ...
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... SPI STATUS REGISTER AT89LS53 14 UART The UART in the AT89LS53 operates the same way as the UART in the AT89C51, AT89C52 and AT89C55. For fur- ther information, see the October 1995 Atmel Microcontrol- ler Data Book, page 2-49, section titled, “Serial Interface.” Serial Peripheral Interface ...
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... There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figures 8 and 9. LSB MISO MISO MOSI MOSI SCK SCK AT89LS53 MSB SLAVE LSB 8-BIT SHIFT REGISTER 15 ...
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... SS (TO SLAVE) *Not defined but normally LSB of previously transmitted character Interrupts The AT89LS53 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. ...
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... The interrupt service routine starts (nomi- nal) after the enabled interrupt pin is activated. ALE PSEN PORT0 1 1 Data 1 1 Float 0 0 Data 0 0 Float AT89LS53 is restored to CC PORT1 PORT2 PORT3 Data Data Data Data Address Data Data Data Data Data Data ...
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... Program Memory Lock Bits The AT89LS53 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ...
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... Turn V power off. CC DATA Polling The AT89LS53 features DATA Polling to indicate the end of a write cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last byte writ- ten will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode) ...
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... Serial Programming Algorithm To program and verify the AT89LS53 in the serial program- ming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between V and GND pins. CC Set RST pin to “H” crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait for at least 10 milliseconds ...
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... P3.4 is pulled Low during programming to indicate RDY/BSY. 3. “X” = don’t care 0851C–MICRO–3/06 RST PSEN ALE/PROG EA ( 12V H L 12V 12V H L 12V 12V 12V 12V ( 12V ( 12V 12V AT89LS53 Data I/O P2.6 P2.7 P3.6 P3.7 P0.7 DIN DOUT DIN DOUT @P0.2 @P0.1 @P0 DOUT DOUT ...
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... Figure 13. Programming the Flash Memory Figure 15. Verifying the Flash Memory AT89LS53 22 Figure 14. Flash Serial Downloading + 0851C–MICRO–3/06 ...
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... GLGH t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC 0851C–MICRO–3/06 PP AT89LS53 Min Max Units 11.5 12 MHz 48t CLCL 48t CLCL 48t CLCL ...
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... Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.7 SERIAL DATA INPUT MOSI/P1.5 SERIAL DATA OUTPUT MISO/P1.6 AT89LS53 LSB MSB LSB MSB 0851C–MICRO–3/06 ...
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... IN 0.45 < V < Test Freq MHz 25°C A Active Mode, 12 MHz Idle Mode, 12 MHz Maximum total related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V AT89LS53 Min Max -0.5 0 0.1 CC -0.5 0 0 0.5 0.5 2 ...
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... ALE Low Low LLWL t Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89LS53 26 12MHz Oscillator Variable Oscillator Min Max Min 0 127 CLCL CLCL CLCL ...
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... External Program Memory Read Cycle External Data Memory Read Cycle 0851C–MICRO–3/06 AT89LS53 27 ...
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... External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89LS53 2.7V to 6.0V CC Min Max 0851C–MICRO–3/06 Units MHz ...
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... CLCL 2t - 117 CLCL 0 700 10t CLCL (1) 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V /V level occurs AT89LS53 Units µ 133 ns 29 ...
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... TYPICAL ICC (IDLE) at 25°C 4.8 4 2.4 m 1.6 A 0.8 0 (MHz) AT89LS53 30 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85° µ 3. 3. Notes AT89LS53 4.0V 5.0V V VOLTAGE CC XTAL1 tied to GND for I (power down) CC Lock bits programmed 0851C–MICRO–3/06 6.0V ...
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... Supply 12 2.7V to 6.0V AT89LS53-12AC AT89LS53-12JC AT89LS53-12PC 2.7V to 6.0V AT89LS53-12AI AT89LS53-12JI AT89LS53-12PI 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 0851C–MICRO–3/06 Package ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LS53 TITLE 44A, 44-lead Body Size, 1 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0851C–MICRO–3/06 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89LS53 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
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... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LS53 34 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...