AT90S8515A-4JC Atmel, AT90S8515A-4JC Datasheet - Page 59
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AT90S8515A-4JC
Manufacturer Part Number
AT90S8515A-4JC
Description
IC MCU 8K FLSH 4MHZ LV 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheets
1.AT90S8515-4AC.pdf
(112 pages)
2.AT90S8515-4AC.pdf
(4 pages)
3.AT90S8515-4AC.pdf
(4 pages)
Specifications of AT90S8515A-4JC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Analog Comparator
Analog Comparator Control
and Status Register – ACSR
0841G–09/01
The Analog Comparator compares the input values on the positive input PB2 (AIN0) and
negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher
than the voltage on the negative input PB3 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator’s output can be set to trigger the Timer/Counter1
Input Capture function. In addition, the comparator can trigger a separate interrupt,
exclusive to the Analog Comparator. The user can select interrupt triggering on compar-
ator output rise, fall or toggle. A block diagram of the comparator and its surrounding
logic is shown in Figure 41 .
Figure 41. Analog Comparator Block Diagram
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in active and idle mode. When changing the ACD bit, the Analog Comparator
interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and will always read as zero.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag. Observe however, that if another bit in this register is modified
Bit
$08 ($28)
Read/Write
Initial Value
ACD
R/W
7
0
R
6
–
0
ACO
N/A
R
5
R/W
ACI
4
0
ACIE
R/W
3
0
ACIC
R/W
2
0
ACIS1
R/W
1
0
AT90S8515
ACIS0
R/W
0
0
ACSR
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